ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet
ATTINY167-15XD
Specifications of ATTINY167-15XD
Related parts for ATTINY167-15XD
ATTINY167-15XD Summary of contents
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... Speed Grade: – MHz @ 2.7 - 5.5V (Automotive Temp. Range: -40°C to +125°C) – MHz @ 4.5 - 5.5V (Automotive Temp. Range: -40°C to +125°C) ® 8-Bit Microcontroller 8-bit Microcontroller with 8K/16K Bytes In-System Programmable Flash and LIN Controller ATtiny87 ATtiny167 Automotive 7728G–AVR–06/10 ...
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... Description 1.1 Comparison Between ATtiny87 and ATtiny167 ATtiny87 and ATtiny167 are hardware and software compatible. They differ only in memory sizes as shown in Table 1-1. Device ATtiny167 ATtiny87 1.2 Part Description The ATtiny87/167 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny87/167 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed ...
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... Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min. and Max val- ues will be available after the device is characterized. 7728G–AVR–06/10 Temperature Grade Identification for Automotive Products Temperature Identifier Comments Z Grade 1 D Grade 0 ATtiny87/ATtiny167 3 ...
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... Block Diagram Figure 1-1. ATtiny87/ATtiny167 4 Block Diagram Watchdog Power Timer Supervision POR / BOD & Watchdog RESET Oscillator Oscillator Flash Circuits / Clock Generation EEPROM Timer/Counter-1 Timer/Counter-0 SPI & USI Analog Comp. PORT B (8) PORT A (8) PB[0..7] PA[0..7] debugWIRE PROGRAM LOGIC SRAM ...
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... PB5 (PCINT13 / ADC8 / OC1BW / XTAL2 / CLKO PB6 (PCINT14 / ADC9 / OC1AX / INT0 PB7 (PCINT15 / ADC10 / OC1BX / RESET / dW 32-lead 21 GND 4 AVCC 20 VCC AGND 5 top view nc 19 PB4 (PCINT12 / OC1AW / XTAL1 / CLKI PB5 (PCINT13 / ADC8 / OC1BW / XTAL2 / CLKO Bottom pad should be soldered to ground ATtiny87/ATtiny167 5 ...
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... These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling compiler dependent. Please confirm with the C com- piler documentation for more details. ATtiny87/ATtiny167 6 76. 81. ...
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... Register File – in one clock cycle. 7728G–AVR–06/10 Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATtiny87/ATtiny167 Data Bus 8-bit Status and Control Interrupt Unit General Watchdog Purpose Timer Registrers A.D.C. ...
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... Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. ATtiny87/ATtiny167 8 7728G–AVR–06/10 ...
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... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 7728G–AVR–06/ R/W R/W R/W R ATtiny87/ATtiny167 R/W R/W R/W R SREG 9 ...
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... The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indi- rect address registers X, Y, and Z are defined as described in ATtiny87/ATtiny167 10 shows the structure of the 32 general purpose working registers in the CPU. ...
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... R31 (0x1F SP15 SP14 SP13 SP12 SP7 SP6 SP5 SP4 R/W R/W R/W R/W R/W R/W R/W R/W ISRAM end (See Table 3-1 on page ATtiny87/ATtiny167 R26 (0x1A R28 (0x1C R30 (0x1E SP11 SP10 SP9 SP8 SP3 SP2 SP1 SP0 R/W ...
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... The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. ATtiny87/ATtiny167 12 CPU shows the parallel instruction fetches and instruction executions enabled by the ...
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... EEPROM write EECR, EEPE sbi out SREG, r16 ; restore SREG value (I-bit) char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMPE); /* start EEPROM write */ EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */ ATtiny87/ATtiny167 13 ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATtiny87/ATtiny167 14 sei ; set Global Interrupt Enable sleep ...
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... ISRAM size 512 bytes ISRAM start 0x0100 ISRAM end 0x02FF E2 size 512 bytes - 0x0000 E2 end 0x01FF 15). Since all AVR instructions are bits Section 20.2.1 “Store Program Memory Control for more details. contains a detailed description on Flash data ATtiny167 16 K bytes (1) 0x3FFF (2) 0x1FFF Sec- 15 ...
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... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers and the internal data SRAM in the ATtiny87/167 are all accessible through all these addressing modes. The Register File is described in ATtiny87/ATtiny167 16 12. Program Memory Map Program Memory shows how the ATtiny87/167 SRAM Memory is organized ...
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... Internal SRAM (ISRAM size) On-chip Data SRAM Access Cycles T1 clk CPU Address Compute Address Data WR Data RD Memory Access Instruction ATtiny87/ATtiny167 0x0000 - 0x001F 0x0020 - 0x005F 0x0060 - 0x00FF ISRAM start ISRAM end cycles as described in Figure CPU T2 T3 Address valid Next Instruction Table 3-1 on page contains a detailed description on EEPROM 3-3 ...
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... If the location to be written has not been erased before write, the data that is stored must be considered as lost. While the device is busy with programming not possible to do any other EEPROM operations. ATtiny87/ATtiny167 18 “Preventing EEPROM Corruption” on page 20 “Atomic Byte Programming” on page 18 Table 3-2 ...
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... Set Programming mode */ EECR = (0<<EEPM1)|(0<<EEPM0); /* Set up address and data registers */ EEAR = ucAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); } ATtiny87/ATtiny167 “OSCCAL – Oscillator Calibration Register” ...
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... First, a regular write sequence to the EEPROM requires a minimum voltage to operate cor- rectly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low. EEPROM data corruption can easily be avoided by following this design recommendation: ATtiny87/ATtiny167 20 EEPROM_read: ; Wait for completion of previous write ...
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... Register Description 3.5.1 EEARH and EEARL – EEPROM Address Register Bit Bit Read/Write Read/Write Initial Value Initial Value 7728G–AVR–06/10 268 EEAR7 EEAR6 EEAR5 R/W R/W R ATtiny87/ATtiny167 Section 25. “Register Summary” EEAR4 EEAR3 EEAR2 EEAR1 R/W R/W R/W R EEAR8 ...
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... EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 3-2. EEPM1 ATtiny87/ATtiny167 22 For information only - ATtiny47: EEAR8 exists as register bit but it is not used for addressing EEDR7 EEDR6 EEDR5 ...
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... GPIOR26 GPIOR25 GPIOR24 R/W R/W R/W R GPIOR17 GPIOR16 GPIOR15 GPIOR14 R/W R/W R/W R GPIOR07 GPIOR06 GPIOR05 GPIOR04 R/W R/W R/W R ATtiny87/ATtiny167 GPIOR23 GPIOR22 GPIOR21 GPIOR20 R/W R/W R/W R GPIOR13 GPIOR12 GPIOR11 GPIOR10 R/W R/W R/W R GPIOR03 GPIOR02 GPIOR01 GPIOR00 R/W R/W ...
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... Figure 4-1. Asynchronous Timer/Counter0 ATtiny87/ATtiny167 24 presents the principal clock systems in the AVR and their distribution. All of the and “Dynamic Clock Switch” on page Clock Distribution ...
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... External Crystal/Ceramic Resonator (8.0 - 16.0 MHz) Notes: 7728G–AVR–06/10 ASY Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. 2. Flash Fuse bits. 3. CLKSELR register bits. ATtiny87/ATtiny167 (1) vs. PB4 and PB5 Functionality (2) CKSEL3..0 (3) CSEL3..0 PB4 0000 ...
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... The Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out even when this Oscillator is used as the device clock. For more information on the pre-pro- grammed calibration value, see the section ATtiny87/ATtiny167 26 Table 4-2. Number of Watchdog Oscillator Cycles Typ ...
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... Power-down/save ( Flash Fuse bits 2. CLKSELR register bits 3. This setting is only available if RSTDISBL fuse is not set ATtiny87/ATtiny167 (1) (MHz) Additional Delay from Reset (Vcc = 5.0V) Recommended Usage 14CK BOD enabled 14CK + 4.1 ms Fast rising power 14CK + 65 ms Slowly rising power Reserved Table 4-1 on page 25 ...
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... The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by CKSEL3..1 fuses or by CSEL3..1 field as shown in Table Table 4-6. CKSEL3..1 CSEL3..1 Notes: ATtiny87/ATtiny167 28 Table 4-6. For ceramic resonators, the capacitor values given Crystal Oscillator Connections C2 C1 4-6 ...
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... They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. 5. This setting is only available if RSTDISBL fuse is not set. 25. The crystal should be connected as shown in ATtiny87/ATtiny167 4-7. Additional Delay from Reset (Vcc = 5.0V) ...
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... When this clock source is selected, start-up times are determined by the SUT Fuses or CSUT field as shown in This external clock can be used by the asynchronous timer if the high or low frequency Crystal Oscillator is not running timer is then able to enable this input. ATtiny87/ATtiny167 30 Low-frequency Crystal Oscillator Connections C1=12-22 pF 32.768 KHz ...
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... Additional delay (+ 4ms) available if RSTDISBL fuse is set. for details. 38.): – ‘Disable Clock Source’, – ‘Enable Clock Source’, – ‘Request Clock Availability’, – ‘Clock Source Switching’, ATtiny87/ATtiny167 Additional Delay from Reset (Vcc = 5.0V) Recommended Usage (3) 14CK (+ 4 BOD enabled 14CK + 4 ...
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... CLKSELR register. CSEL3..0 will select the clock source and CSUT1:0 will select the start-up time (just as CKSEL and SUT fuse bits do sure that a clock source is operating, the ‘Request for Clock Availability ’ command must be executed after the ‘Enable ATtiny87/ATtiny167 32 – ‘Recover System Clock Source’, – ...
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... Once this command has been successfully completed using the ‘Recover System Clock Source’ command, the user (code) may stop the previous clock source. 7728G–AVR–06/10 for using. Table 4-1 on page 25. The CKSEL field of CLKSELR register is then ATtiny87/ATtiny167 Section 4.2.7 “Clock Output 33 ...
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... Clock Monitoring A safe system needs to monitor its clock sources. Two domains need to be monitored: - Clock sources for peripherals, - Clocks sources for system clock generation. ATtiny87/ATtiny167 34 void ClockSwiching (unsigned char clk _ #define CLOCK RECOVER ...
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... ONLY the reset (watchdog reset included) disables this function. The Watchdog System Reset Flag (WDRF bit of MCUSR register) can be used to monitor the reset cause. 2. ONLY clock frequencies greater than or equal WatchDog Clock Frequency) can be monitored. ATtiny87/ATtiny167 WatchDog Clock Reload Automatic Reloading ...
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... Here is a “light” C-code of a clock switching function using automatic clock monitoring. C Code Example ATtiny87/ATtiny167 36 void ClockSwiching (unsigned char clk _ #define CLOCK RECOVER 0x05 _ #define CLOCK ENABLE 0x02 _ #define CLOCK SWITCH 0x04 _ #define CLOCK DISABLE 0x01 _ _ #define WD ARL ENABLE ...
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... Table 4-10 on page CAL7 CAL6 CAL5 CAL4 R/W R/W R/W R/W Device Specific Calibration Value ATtiny87/ATtiny167 , clk , clk , and clk I/O ADC CPU 39 CAL3 CAL2 CAL1 CAL0 ...
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... Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. ATtiny87/ATtiny167 CLKPCE – ...
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... The delay from the request and the flag setting is not fixed, it depends on the clock 7728G–AVR–06/10 Clock Prescaler Select CLKPS2 CLKPS1 CLKCCE – – R ATtiny87/ATtiny167 CLKPS0 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved CLKRDY CLKC3 CLKC2 CLKC1 R R/W R/W R CLKC0 CLKCSR R ...
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... The COUT bit is initialized with ~(CKOUT) Fuse bit. The COUT bit is only used in case of ‘CKOUT’ command. Refer to Buffer” on page 31 In case of ‘Recover System Clock Source’ command, COUT it is not affected (no recovering of this setting). ATtiny87/ATtiny167 40 39.). CLKCSR to zero. bit. ...
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... In case of ‘Recover System Clock Source’ command, CSEL field contains the code of the clock source used to drive the Clock Control Unit as described in 7728G–AVR–06/10 Section 4.2 “Clock Sources” on page 25 and subdivisions of Section 4.2 “Clock Sources” on page 25 ATtiny87/ATtiny167 for code of Table 4-1 on for clock source codes. Figure 4-1 on page 24. ...
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... SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. ATtiny87/ATtiny167 42 “BOD Disable” on page 43 for more details ...
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... Watchdog Interrupt, a Brown-out Reset, a USI start condition interrupt, an asynchronous Timer/Counter interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or INT1 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode. 7728G–AVR–06/10 ATtiny87/ATtiny167 47. Setting it to one turns off the BOD in relevant 47. and clk , while allowing the other clocks to run ...
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... PRR, puts the module in the same state as before shutdown. Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped. ATtiny87/ATtiny167 44 for details. Section 4.2 “Clock Sources” on page ...
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... ADC operation. Section 18. “AnaComp - Analog Comparator” on page for details on how to configure the Brown-out Detector. ATtiny87/ATtiny167 Section 17. “ADC – Analog to Digital Con- Section 6.1.5 “Brown-out Detection” on for details on the start-up time. for details on how to disable the inter- “ ...
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... These bits are unused bits in the ATtiny87/167, and will always read as zero. • Bits 2..1 – SM1..0: Sleep Mode Select Bits 1, and 0 These bits select between the four available sleep modes as shown in ATtiny87/ATtiny167 46 Section 6.3 “Watchdog Timer” on page 53 ) and the ADC clock (clk ...
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... ADC Noise Reduction 1 0 Power-down 1 1 Power-save – BODS BODSE R R/W R 42. Writing to the BODS bit is controlled by a timed sequence and an enable bit – – PRLIN ATtiny87/ATtiny167 PUD – – – R PRSPI PRTIM1 PRTIM0 PRUSI R/W R/W R/W R – ...
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... USI again, the USI should be re-initialized to ensure proper operation. • Bit 0 - PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. ATtiny87/ATtiny167 48 7728G–AVR–06/10 ...
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... Brown-out Reset. The MCU is reset when the supply voltage Vcc is below the Brown-out Reset threshold (V 7728G–AVR–06/10 Figure 6-1 shows the reset circuit. Tables in defines the electrical parameters of the reset circuitry. 25. ). POT ) and the Brown-out Detector is enabled. BOT ATtiny87/ATtiny167 Section 22.5 Section 4.2 “Clock 49 ...
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... Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after Vcc rise. The RESET signal is activated again, without any delay, when Vcc decreases below the detection level. Figure 6-2. TIME-OUT INTERNAL RESET ATtiny87/ATtiny167 50 Reset Circuit Power-on Reset Circuit Brown-out Reset Circuit ...
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... Figure 6-5), the delay counter starts the MCU after the Time-out period t BOT + given in Table 22-6 on page BOD ATtiny87/ATtiny167 V RST t TOUT 246) will generate a reset, even if the clock is – on its positive edge, the delay counter starts RST – has expired. The External Reset can be disabled 226 ...
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... This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. ATtiny87/ATtiny167 52 Brown-out Reset During Operation V CC ...
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... Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 6.3.1 Watchdog Timer Behavior The Watchdog Timer (WDT timer counting cycles of a separate on-chip 128 KHz oscillator. 7728G–AVR–06/10 Table 22-7 on page ACIRS bit in ACSR). ATtiny87/ATtiny167 247. To save power, the reference is not always 53 ...
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... Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows the same operation, write a logic one to the Watchdog change enable bit (WDCE) 2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) ATtiny87/ATtiny167 54 Watchdog Timer ~128 KHz ...
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... WDT_off(void) { __disable_interrupt(); __watchdog_reset(); /* Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; __enable_interrupt(); } 1. See ”About Code Examples” on page 6. ATtiny87/ATtiny167 55 ...
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... C Code Example Notes: 6.3.2 Clock monitoring The Watchdog Timer can be used to detect a loss of system clock. This configuration is driven by the dynamic clock switch circuit. Please refer to 34 for more information. ATtiny87/ATtiny167 56 (1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ...
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... Off least one of these three enables (WDTON, WDE & WDIE) equal to 1. ATtiny87/ATtiny167 WDCE WDE WDP2 WDP1 R/W R/W R/W R Section • “Bits 3:0 – CLKC3:0: Clock Con- Action on Time-out Stopped None System Reset Mode Reset Interrupt Mode Interrupt System Reset Mode ...
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... The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are shown in Table 6-2 on page Table 6-2. WDP3 ATtiny87/ATtiny167 58 58. Watchdog Timer Prescale Select WDP2 WDP1 WDP0 WDT Oscillator Cycles 16K (16384) cycles ...
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... LIN TC LIN/UART Transfer Complete LIN ERR LIN/UART Error SPI, STC SPI Serial Transfer Complete ADC ADC Conversion Complete EE READY EEPROM Ready ANALOG COMP Analog Comparator Start Condition Detection USI START USI USI OVF USI Counter Overflow ATtiny87/ATtiny167 “Reset and Interrupt Han- 59 ...
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... RESET: 0x0015 0x0016 0x0017 0x0018 0x0019 Note: ATtiny87/ATtiny167 60 (Note:) Label Code rjmp RESET rjmp INT0addr rjmp INT1addr rjmp PCINT0addr rjmp PCINT1addr rjmp WDTaddr rjmp ICP1addr rjmp OC1Aaddr ...
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... Program Setup in ATtiny167 The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny167 is (4-byte step - using “jmp” instruction): Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C ...
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... CKSEL Fuses as described in 8.2 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 8-1. ATtiny87/ATtiny167 62 24. Low level interrupts and the edge interrupt on INT1..0 are detected asynchronously. “Clock Systems and their Distribution” on page Timing of pin change interrupts ...
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... The low level of INTn generates an interrupt request Any logical change on INTn generates an interrupt request The falling edge of INTn generates an interrupt request The rising edge of INTn generates an interrupt request. Bit – – – ATtiny87/ATtiny167 – ISC11 ISC10 ISC01 R R/W R/W R – – ...
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... Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. 8.3.4 Pin Change Interrupt Control Register – PCICR Read/Write Initial Value • Bit 7, 2 – Res: Reserved Bits These bits are unused bits in the ATtiny87/167, and will always read as zero. ATtiny87/ATtiny167 64 Bit – – ...
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... I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 7728G–AVR–06/10 Bit – – – Bit PCINT15 PCINT14 PCINT13 R/W R/W R ATtiny87/ATtiny167 – – – PCIF1 R PCINT12 PCINT11 PCINT10 PCINT9 R/W R/W R/W R/W ...
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... Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. ATtiny87/ATtiny167 66 Bit 7 ...
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... Characteristics” on page 243 I/O Pin Equivalent Schematic Pxn C pin 86. 72. Refer to the individual module sections for a full description of the ATtiny87/ATtiny167 for a complete list of parameters Logic See Figure "General Digital I/O" for Details “Register Description for I/O Ports” on “ ...
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... If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). ATtiny87/ATtiny167 68 (Note:) General Digital I/O ...
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... When switching the DDRxn bit from output to input there is Break Before Make, switching between input and output out DDRx, r16 PORTx DDRx 0x01 Px0 immediate tri-state cycle Px1 tri-state ATtiny87/ATtiny167 0x02 0x01 nop out DDRx, r17 0x55 0x02 tri-state immediate tri-state cycle Figure 9-3. “Port Control ...
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... When reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. ATtiny87/ATtiny167 70 summarizes the control signals for the pin value. Port Pin Configurations ...
Page 71
... For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. ATtiny87/ATtiny167 0xFF nop ...
Page 72
... The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. ATtiny87/ATtiny167 72 Figure 9-2, the digital input signal can be clamped to ground at the input of the “ ...
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... SLEEP: SLEEP CONTROL PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. ATtiny87/ATtiny167 PUD Q D ...
Page 74
... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for fur- ther details. ATtiny87/ATtiny167 74 summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables ...
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... Disable bit (PUD) from the MCUCR register. See details about this feature. 7728G–AVR–06/10 Bit – BODS BODSE R R/W R for more details about this feature. Bit BBMB R/W R/W R “Break-Before-Make Switching” on page ATtiny87/ATtiny167 PUD – – – R BBMA - - PUDB R/W R/W R/W R ...
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... Alternate Functions of Port A The Port A pins with alternate functions are shown in Table 9-3. ATtiny87/ATtiny167 76 Port A Pins Alternate Functions Port Pin Alternate Function PCINT7 (Pin Change Interrupt 7) ADC7 (ADC Input Channel 7) PA7 AIN1 (Analog Comparator Positive Input) XREF (Internal Voltage Reference Output) ...
Page 77
... DDA5. When the pin is forced input, the pull-up can still be controlled by the PORTA5 bit. Timer/Counter1. functions, so pin must be configure as an input for DI function. figured as an input regardless of the setting of DDA3. When the SPI is enabled as a ATtiny87/ATtiny167 77 ...
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... RXLIN: LIN Receive pin. When the LIN is enabled, this pin is configured as an input regard- Table 9-4 in Figure 9-6 on page ATtiny87/ATtiny167 78 Master, the data direction of this pin is controlled by DDA3. When the pin is forced by the SPI input, the pull-up can still be controlled by the PORTA3 bit. ...
Page 79
... PCMSK07) PCMSK06) PCIE0 & PCIE0 & PCMSK07 PCMSK06 PCINT7 PCINT6 -/- SS ADC7 -/- AIN1 -/- ADC6 -/- AIN0 XREF -/- AREF ATtiny87/ATtiny167 PA5/PCINT5/ADC5/ PA4/PCINT4/ADC4/ T1/USCK/SCL/SCK ICP1/DI/SDA/MOSI SPE & MSTR SPE & MSTR PORTA5 & PUD PORTA4 & PUD (SPE & MSTR) | (SPE & MSTR) | (USI_2_WIRE & ...
Page 80
... Table 9-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATtiny87/ATtiny167 80 Overriding Signals for Alternate Functions in PA3..PA0 PA3/PCINT3/ADC3/ PA2/PCINT2/ADC2/ ISRC/INT1 OC0A/DO/MISO 0 SPE & MSTR PORTA3 & PUD PORTA2 & PUD 0 SPE & MSTR 0 0 (SPE & MSTR) | (USI_2_WIRE & ...
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... DI (Three-wire Mode USI Default Data Input) SDA (Two-wire Mode USI Default Data Input / Output) configured as an output (DDB7 set (one)) to serve this function. The OC1BX pin is also the output pin for the PWM mode timer function (c.f. OC1BX bit of TCCR1D regis- ter). ATtiny87/ATtiny167 Table 9-6. 81 ...
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... PCINT11/OC1BV – Port B, Bit 3 PCINT11: Pin Change Interrupt, source 11. OC1BV: Output Compare and PWM Output B-V for Timer/Counter1. The PB3 pin has to be ATtiny87/ATtiny167 82 normal I/O pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its reset sources. When the RSTDISBL Fuse is unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an I/O pin ...
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... PORTB1 is set configured as an output (DDB0 set (one)) to serve this function. The OC1AU pin is also the output pin for the PWM mode timer function (c.f. OC1AU bit of TCCR1D regis- ter). functions, so pin must be configure as an input for DI function. ATtiny87/ATtiny167 one ( ). 83 ...
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... Figure 9-6 on page Table 9-7. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATtiny87/ATtiny167 84 and Table 9-8 relate the alternate functions of Port B to the overriding signals shown 73. Overriding Signals for Alternate Functions in PB7..PB4 PB7/PCINT15/ADC10 / PB6/PCINT14/ADC9/ OC1BX/RESET/dW OC1AX/INT0 ...
Page 85
... DDRB2) ? (0) : (OC1A USI_PTOE & USIPOS PCIE1 & (USISIE & USIPOS) | PCMSK11 (PCIE1 & PCMSK10) (USISIE & USIPOS (PCIE1 & PCMSK10) PCINT10 -/- USCK -/- PCINT11 SCL 0 0 ATtiny87/ATtiny167 PB1/PCINT9/ PB0/IPCINT8/ OC1BU/DO OC1AU/DI/SDA (USI_2_WIRE & 0 USIPOS) (USI_SHIFTOUT | 0 PORTB0) & DDRB0) (USI_2_WIRE & (USI_2_WIRE & ...
Page 86
... Port B Data Register – PORTB Bit Read/Write Initial Value 9.4.5 Port B Data Direction Register – DDRB Bit Read/Write Initial Value 9.4.6 Port B Input Pins Register – PINB Bit Read/Write Initial Value ATtiny87/ATtiny167 PORTA7 PORTA6 PORTA5 PORTA4 R/W R/W R/W R/W 0 ...
Page 87
... I/O pins, refer to including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the 7728G–AVR–06/10 ATtiny87/ATtiny167 “Pin Configuration” on page “8-bit Timer/Counter Register Description” on page Figure 10-1. For the actual 5 ...
Page 88
... The result of the compare can be used by the Waveform Generator to gen- erate a PWM or variable frequency output on the Output Compare pin (OC0A). Compare Unit” on page 90. flag (OCF0A) which can be used to generate an Output Compare interrupt request. ATtiny87/ATtiny167 88 TCCRnx count clear ...
Page 89
... Clear TCNT0 (set all bits to zero). clk 0 Timer/Counter0 clock. T top Signalizes that TCNT0 has reached maximum value. bottom Signalizes that TCNT0 has reached minimum value (zero). ATtiny87/ATtiny167 . When the AS0 bit in the ASSR Regis- I/O 103. For details on clock sources 100. TOVn (Int.Req.) Oscillator clk ...
Page 90
... Compare Output mode (COM0A1:0) bits. The max and bottom signals are used by the Wave- form Generator for handling the special cases of the extreme values in some modes of operation Figure 10-3 Figure 10-3. Output Compare Unit, Block Diagram ATtiny87/ATtiny167 90 0). clk 0 can be generated from an external or internal clock present or not ...
Page 91
... I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM0A1:0 bits are shown. When referring to the OC0A state, the reference is for the internal OC0A Register, not the OC0A pin. 7728G–AVR–06/10 ATtiny87/ATtiny167 Figure 10-4 shows a 91 ...
Page 92
... Waveform Generation mode bits do. The COM0A1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM0A1:0 bits control whether the output should be set, cleared, or tog- gled at a compare match ATtiny87/ATtiny167 92 COMnx1 Waveform ...
Page 93
... TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. 7728G–AVR–06/10 “Timer/Counter Timing Diagrams” on page Figure ATtiny87/ATtiny167 97. 10-5. The counter value (TCNT0) OCnx Interrupt Flag Set (COMnx1 ...
Page 94
... OCR0A and TCNT0. Figure 10-6. Fast PWM Mode, Timing Diagram TCNTn OCnx OCnx Period ATtiny87/ATtiny167 94 /2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the follow- f OCnx Figure 10-6. The TCNT0 value is in the timing diagram shown as a ...
Page 95
... The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0. 7728G–AVR–06/10 ATtiny87/ATtiny167 Table 10-2 on page f clk_I/O f ...
Page 96
... PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. ATtiny87/ATtiny167 96 1 ...
Page 97
... MAX - 1 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O MAX - 1 shows the setting of OCF0A in all modes except CTC mode. I/O Tn /8) I/O OCRnx - 1 ATtiny87/ATtiny167 MAX BOTTOM /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value should be I/O BOTTOM + 1 ...
Page 98
... MCU will not wake up. • If Timer/Counter0 is used to wake the device up from Power-save mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one ATtiny87/ATtiny167 98 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Prescaler (f ...
Page 99
... Wait until the corresponding Update Busy flag in ASSR returns to zero. c. Enter Power-save or ADC Noise Reduction mode. a. Write any value to either of the registers OCR0A or TCCR0A. b. Wait for the corresponding Update Busy Flag to be cleared. c. Read TCNT0. ATtiny87/ATtiny167 ) again becomes active, TCNT0 will read as the I/O 99 ...
Page 100
... These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is con- nected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0A pin must be set in order to enable the output driver. ATtiny87/ATtiny167 100 clk I/O ...
Page 101
... Clear OC0A on Compare Match when down-counting special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See on page 95 for more details. ATtiny87/ATtiny167 (1) “Fast PWM Mode” on page (1) “Phase Correct PWM Mode” ...
Page 102
... OCR0A as TOP. The FOC0A bit is always read as zero. • Bit 6:3 – Res: Reserved Bits These bits are reserved in the ATtiny87/167 and will always read as zero. • Bit 2:0 – CS02:0: Clock Select ATtiny87/ATtiny167 102 92.). Waveform Generation Mode Bit Description WGM01 ...
Page 103
... TCNT05 R/W R/W R OCR0A7 OCR0A6 OCR0A5 R/W R/W R – EXCLK AS0 R R/W R ATtiny87/ATtiny167 Description No clock source (Timer/Counter stopped). clk 0 (No prescaling clk 0 /8 (From prescaler clk 0 /32 (From prescaler clk 0 /64 (From prescaler clk 0 /128 (From prescaler clk 0 /256 (From prescaler) ...
Page 104
... The mechanisms for reading TCNT0, OCR0A, TCCR0A and TCCR0B are different. When reading TCNT0, the actual timer value is read. When reading OCR0A, TCCR0A or TCCR0B the value in the temporary storage register is read. ATtiny87/ATtiny167 104 29.) or from external clock on XTAL1 pin 30.) depending on EXCLK setting. When the value of AS0 is ...
Page 105
... Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00. 7728G–AVR–06/ – – – – – – – – ATtiny87/ATtiny167 – – OCIE0A TOIE0 R R R/W R – – OCF0A TOV0 R R R/W R TIMSK0 TIFR0 105 ...
Page 106
... If the bit is written when Timer/Counter0 is operating in asynchro- nous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the Timer/Counter Synchronization Mode” on page 109 Synchronization mode. ATtiny87/ATtiny167 106 ...
Page 107
... Figure 11-1. T1 Pin Sampling 7728G–AVR–06/10 ). Alternatively, one of four taps from the prescaler can be CLK_I/O /256 /1024. CLK_I clk I/O Synchronization ATtiny87/ATtiny167 CLK_I/O Figure 11-1 clk pulse for each positive (CSn2 negative D Q Edge Detector /8, f /64, CLK_I/O 1). T shows a ). The latch is I/O Tn_sync ...
Page 108
... Oscillator source (crystal, resonator, and capaci- tors) tolerances recommended that maximum frequency of an external clock source is less than f An external clock source can not be prescaled. Figure 11-2. Prescaler for Timer/Counter1 Note: ATtiny87/ATtiny167 108 < f /2) given a 50/50 % duty cycle. Since the edge detec- ExtClk clk_I/O /2 ...
Page 109
... Bit 0 – PSR1: Prescaler Reset Timer/Counter1 When this bit is one, Timer/Counter1 prescaler will be reset. This bit is normally cleared imme- diately by hardware, except if the TSM bit is set. 7728G–AVR–06/ TSM – – – ATtiny87/ATtiny167 – – PSR0 PSR1 GTCCR R R R/W R 109 ...
Page 110
... A simplified block diagram of the 16-bit Timer/Counter is shown in placement of I/O pins, refer to including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the ATtiny87/ATtiny167 110 “Pin Configuration” on page “16-bit Timer/Counter Register Description” on page Figure 12-1 ...
Page 111
... OCRnA = OCRnB ICRn TCCRnA TCCRnB 1. Refer to Figure 1-2 on page 5, Table 9-6 on page Timer/Counter1 pin placement and description. 112. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have ATtiny87/ATtiny167 (1) TOVn (Int.Req.) clk Clock Select Tn Edge Detector BOTTOM ( From Prescaler ) = 0 OCFnA (Int ...
Page 112
... Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-bit registers does not involve using the temporary register 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. ATtiny87/ATtiny167 112 ). T n 119 ...
Page 113
... Set TCNT1 to 0x01FF r17,0x01 ldi ldi r16,0xFF sts TCNT1H,r17 TCNT1L,r16 sts ; Read TCNT1 into r17:r16 r16,TCNT1L lds lds r17,TCNT1H ... (1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into TCNT1; ... 1. The example code assumes that the part specific header file is included. ATtiny87/ATtiny167 113 ...
Page 114
... The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example C Code Example Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. ATtiny87/ATtiny167 114 (1) TIM16_ReadTCNT1: ; Save global interrupt flag r18,SREG in ...
Page 115
... Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg The example code assumes that the part specific header file is included. see “Timer/Counter1 Prescaler” on page ATtiny87/ATtiny167 107. 115 ...
Page 116
... There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC1A/B. For more details about advanced counting sequences and waveform generation, see ATtiny87/ATtiny167 116 Figure 12-2 shows a block diagram of the counter and its surroundings. ...
Page 117
... DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACIC ICPn Canceler ACO Analog Comparator ATtiny87/ATtiny167 Figure 12-3. The elements (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNCn ICESn Noise Edge ICF1n (Int.Req.) Detector ...
Page 118
... Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 flag is not required (if an interrupt handler is used). ATtiny87/ATtiny167 118 112. ...
Page 119
... Output Compare unit. The elements of the block dia- DATA BUS TEMP (8-bit) OCRnxH Buf.(8-bit) OCRnxL Buf.(8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATtiny87/ATtiny167 (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 COMnx1:0 122 ...
Page 120
... The Compare Output mode (COM1A/B1:0) bits have two functions. The Waveform Generator uses the COM1A/B1:0 bits for defining the Output Compare (OC1A/B) state at the next com- pare match. Secondly the COM1A/B1:0 and OCnxi bits control the OC1A/Bi pin output source. ATtiny87/ATtiny167 120 112. ...
Page 121
... OCR1A COM1A0 16-bit Register COM1A1 OCF1A Waveform = Generation WGM10 TCNT1 WGM11 WGM12 16-bit Counter WGM13 Waveform = Generation OCF1B COM1B0 COM1B1 OCR1B 16-bit Register ( ) OC1xi: TCCR1D register bit * ATtiny87/ATtiny167 OC1AU ( ) * PINB0 1 PORTB0 0 DDB0 OC1AV ( ) * PINB2 1 PORTB2 0 DDB2 OC1AW ( ) * PINB4 1 PORTB4 0 DDB4 OC1AX ( ...
Page 122
... Output mode (COM1A/B1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1A/B1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1A/B1:0 bits control whether the output should be set, cleared ATtiny87/ATtiny167 122 OCnxi COMnx1 ...
Page 123
... Match Output Unit” on page TCNTn OCnAi (Toggle) Period 1 2 ATtiny87/ATtiny167 Figure 12-6 on page “Timer/Counter Timing Diagrams” on page Figure 12-7. The counter value (TCNT1) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 ...
Page 124
... The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: ATtiny87/ATtiny167 124 when OCR1A is set to zero (0x0000) ...
Page 125
... TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 flag is set. 7728G–AVR–06/ ATtiny87/ATtiny167 OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...
Page 126
... The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: ATtiny87/ATtiny167 126 f clk_I/O ...
Page 127
... TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. 7728G–AVR–06/10 ATtiny87/ATtiny167 Figure 12-9 ...
Page 128
... ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: ATtiny87/ATtiny167 128 133). The actual OC1A/B value will only be visible on the port pin if the data direction for ...
Page 129
... Figure 12-10. The figure shows phase and frequency shows the output generated is, in contrast to the phase correct mode, sym- ATtiny87/ATtiny167 OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) ...
Page 130
... OCR1A/B Register is updated with the OCR1A/B buffer value (only for modes utilizing double buffering). of OCF1A/B. Figure 12-11. Timer/Counter Timing Diagram, Setting of OCF1A/B, no Prescaling Figure 12-12 ATtiny87/ATtiny167 130 Table on page 133). The actual OC1A/B value will only be visible on the port pin f ...
Page 131
... TOP - 1 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) shows the same timing data, but with the prescaler enabled. ATtiny87/ATtiny167 OCRnx + 1 OCRnx + 2 OCRnx Value TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value ...
Page 132
... When the OC1Ai or OC1Bi is connected to the pin, the function of the COM1A/B1:0 bits is dependent of the WGM13:0 bits setting. when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM). Table 12-1. OC1Ai OC1Bi 0 1 ATtiny87/ATtiny167 132 clk I/O clk Tn (clk /8) I/O ...
Page 133
... Set OC1A/OC1B on Compare Match when downcounting. Set OC1A/OC1B on Compare Match when up-counting Clear OC1A/OC1B on Compare Match when downcounting special case occurs when OC1A/OC1B equals TOP and COM1A1/COM1B1 is set. “Phase Correct PWM Mode” on page 126. ATtiny87/ATtiny167 (1) See “Fast PWM for more details. See 133 ...
Page 134
... Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATtiny87/ATtiny167 134 (1) WGM10 Timer/Counter (PWM10) Mode of Operation 0 0 Normal 0 1 PWM, Phase Correct, 8-bit ...
Page 135
... I clk /64 (From prescaler) I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge. ATtiny87/ATtiny167 WGM12 CS12 CS11 CS10 R/W R/W R/W R TCCR1B Fig- 135 ...
Page 136
... Bit 7:4 – OC1Bi: Output Compare Pin Enable for Channel B The OC1Bi bits enable the Output Compare pins of Channel B as shown in page • Bit 3:0 – OC1Ai: Output Compare Pin Enable for Channel A The OC1Ai bits enable the Output Compare pins of Channel A as shown in page ATtiny87/ATtiny167 136 FOC1A FOC1B – ...
Page 137
... TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R See “Accessing 16-bit Registers” on page 112. ATtiny87/ATtiny167 R/W R/W R/W R See “Accessing R/W R/W R/W R R/W R/W R/W R TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ...
Page 138
... Bit 0 – TOIE1: Timer/Counter Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vec- tor (See ”Interrupt Vectors in ATtiny87/167” on page located in TIFR1, is set. ATtiny87/ATtiny167 138 R/W ...
Page 139
... TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is exe- cuted. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 7728G–AVR–06/ – – ICF1 – R ATtiny87/ATtiny167 – OCF1B OCF1A TOV1 TIFR1 R R/W R/W R Table 12-4 on page 134 for the TOV1 ...
Page 140
... End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode Figure 13-1. SPI Block Diagram /2/4/8/16/32/64/128 Note: ATtiny87/ATtiny167 140 (1) clk IO DIVIDER 1. Refer to Figure 1.6 on page 5, and Table 9-3 on page 76 for SPI pin placement. ...
Page 141
... Otherwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the frequency of the SPI clock should never exceed f /4. clkio 7728G–AVR–06/10 ATtiny87/ATtiny167 Figure 13-2. The SHIFT ENABLE 141 ...
Page 142
... SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direc- tion bits for these pins. E.g. if MOSI is placed on pin PB2, replace DD_MOSI with DDB2 and DDR_SPI with DDRB. ATtiny87/ATtiny167 142 Table 13-1. For more details on automatic port overrides, refer to 72 ...
Page 143
... Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } void SPI_MasterTransmit(char cData Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))); } 1. The example code assumes that the part specific header file is included. ATtiny87/ATtiny167 143 ...
Page 144
... The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example C Code Example Note: ATtiny87/ATtiny167 144 (1) SPI_SlaveInit: ; Set MISO output, all others input r17,(1<<DD_MISO) ldi DDR_SPI,r17 out ; Enable SPI ldi r17,(1<<SPE) ...
Page 145
... When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. 7728G–AVR–06/10 of the SPI becoming a Slave, the MOSI and SCK pins become inputs. SREG is set, the interrupt routine will be executed SPIE SPE DORD R/W R/W R ATtiny87/ATtiny167 MSTR CPOL CPHA SPR1 R/W R/W R/W R ...
Page 146
... Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the clk shown in the following table: Table 13-4. ATtiny87/ATtiny167 146 Figure 13-3 and CPOL Functionality ...
Page 147
... Table 13-4). This means that the minimum SCK period will be two “Serial Downloading” on page 238 SPD7 SPD6 SPD5 SPD4 R/W R/W R/W R ATtiny87/ATtiny167 – – – SPI2X R for serial programming and SPD3 SPD2 SPD1 SPD0 SPDR R/W R/W ...
Page 148
... SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by sum- marizing Table 13-5. Figure 13-3. SPI Transfer Format with CPHA = 0 Figure 13-4. SPI Transfer Format with CPHA = 1 ATtiny87/ATtiny167 148 and Figure 13-4. Data bits are shifted out and latched in on opposite edges of the ...
Page 149
... Configuration” on page 5. CPU accessible I/O Registers, including I/O bits 156 USIDR 1 TIM0 COMP 0 USIDB 4-bit Counter [1] USISR 2 USICR ATtiny87/ATtiny167 Figure 14-1 For the actual placement of I/O (Output only) DO (Input/Open Drain) DI/SDA (Input/Open Drain) USCK/SCL CLOCK HOLD Two-wire Clock Control Unit 149 ...
Page 150
... Slave. The two USI Data Register are interconnected in such way that after eight USCK clocks, the data in each register are interchanged. The same clock also increments the USI’s 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a transfer is completed. ATtiny87/ATtiny167 150 Bit7 Bit6 ...
Page 151
... The overflow interrupt will wake up the proces- sor set to Idle mode. Depending of the protocol used the slave device can now set its output to high impedance. USIDR,r16 sts ldi r16,(1<<USIOIF) sts USISR,r16 ldi r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC) ATtiny87/ATtiny167 ...
Page 152
... The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. The following code demonstrates how to use the USI module as a SPI Master with maximum speed (fsck = fck/4): SPITransfer_Fast: ATtiny87/ATtiny167 152 sts USICR,r16 lds ...
Page 153
... Pin names used by this mode are SCL and SDA. 7728G–AVR–06/10 r16,(1<<USIWM0)|(1<<USICS1) ldi sts USICR,r16 USIDR,r16 sts ldi r16,(1<<USIOIF) sts USISR,r16 r16, USISR lds sbrs r16, USIOIF rjmp SlaveSPITransfer_loop lds r16,USIDR ret ATtiny87/ATtiny167 153 ...
Page 154
... The clock is generated by the master by toggling the USCK pin via the PORT Register. The data direction is not given by the physical layer. A protocol, like the one used by the TWI-bus, must be implemented to control the data flow. Figure 14-5. Two-wire Mode, Typical Timing Diagram SDA SCL ATtiny87/ATtiny167 154 Bit7 Bit6 Bit5 Bit4 Bit3 ...
Page 155
... SDA line) The slave can hold the SCL line low after the acknowledge (E). given by the Master (F new start condition is given. SDA SCL Write( USISIF) “Clock Systems and their Distribution” on page ATtiny87/ATtiny167 14-5), a bus transfer involves the following steps: USISIF CLOCK ...
Page 156
... The output will be changed immediately when a new MSB written as long as the latch is open. The latch ensures that data input is sampled and data output is changed on opposite clock edges. ATtiny87/ATtiny167 156 7 6 ...
Page 157
... Two-wire bus master arbitration. 7728G–AVR–06/ USIB7 USIB6 USIB5 USIB4 USISIF USIOIF USIPF USIDC R/W R/W R & USICLK = 0), any edge on the SCK pin sets the flag. b ATtiny87/ATtiny167 USIB3 USIB2 USIB1 USIB0 USICNT3 USICNT2 USICNT1 USICNT0 R/W R/W R/W R USIBR USISR & ...
Page 158
... Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and USI Data Register can therefore be clocked externally, and data input sampled, even when outputs are disabled. The relations between USIWM1:0 and the USI operation is summarized in ATtiny87/ATtiny167 158 7 6 ...
Page 159
... Counter Overflow Flag (USIOIF) is cleared. 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respec- tively to avoid confusion between the modes of operation. shows the relationship between the USICS1..0 and USICLK setting ATtiny87/ATtiny167 (1) . 159 ...
Page 160
... When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detec- tion of when the transfer is done when operating as a master device. ATtiny87/ATtiny167 160 Relations between the USICS1..0 and USICLK Setting ...
Page 161
... Setting or clearing this bit changes the USI pin position. Table 14- 7728G–AVR–06/ USI Pin Position USIPOS USI Pin Position DI, SDA PB0 - (PCINT8/OC1AU) PortB DO PB1 - (PCINT9/OC1BU) (Default) USCK, SCL PB2 - (PCINT10/OC1AV) DI, SDA PA4 - (PCINT4/ADC4/ICP1/MOSI) Port A DO PA2 - (PCINT2/ADC2/OC0A/MISO) (Alternate) USCK, SCL PA5 - (PCINT5/ADC5/T1/SCK) ATtiny87/ATtiny167 USIPOS USIPP R/W 0 161 ...
Page 162
... Full Duplex Operation (Independent Serial Receive and Transmit Processes) • Asynchronous Operation • High Resolution Baud Rate Generator • Hardware Support of 8 Data Bits, Odd/Even/No Parity Bit, 1 Stop Bit Frames • Data Over-Run and Framing Error Detection ATtiny87/ATtiny167 162 7728G–AVR–06/10 ...
Page 163
... LIN bus HEADER RESPONSE FRAME SLOT PROTECTED IDENTIFIER DATA-0 Field Field Response Space ATtiny87/ATtiny167 slave node 1 n slave task HEADER RESPONSE RESPONSE DATA-n CHECKSUM Field Field Inter-Byte Space Each byte field is transmitted as a serial byte, LSB first. ...
Page 164
... Tx LIN Header function, • Rx LIN Header function, • LIN Response function. These functions mainly use two services: • Rx service, • Tx service. Because these two services are basically UART services, the controller is also able to switch into an UART function. ATtiny87/ATtiny167 164 7728G–AVR–06/10 ...
Page 165
... The UART has an enhanced baud rate generator providing a maximum error of 2% whatever the clock frequency and the targeted baud rate. 7728G–AVR–06/10 ATtiny87/ATtiny167 Section 15.3.4 on page 164). The ATtiny87/167 con- 165 ...
Page 166
... LIN/UART Controller Structure Figure 15-4. LIN/UART Controller Block Diagram CLK IO RxD 15.4.4 LIN/UART Command Overview Figure 15-5. LIN/UART Command Dependencies ATtiny87/ATtiny167 166 Prescaler Sample /bit BAUD_RATE Get Byte Frame Time-out RX Synchronization Monitoring Data FIFO Tx Header IDOK Rx Header LIN Abort Automatic ...
Page 167
... Table 15-1 on page 167, four functions controlled by the LCMD[1..0] bits of Figure 15-5 on page (See ”Break-in-data” on page ATtiny87/ATtiny167 Command Comment Disable peripheral Rx Header - LIN Abort LIN Withdrawal Tx Header LCMD[2..0]=000 after Tx Rx Response LCMD[2..0]=000 after Rx Tx Response LCMD[2..0]=000 after Tx ...
Page 168
... While the controller is sending or receiving a response, BREAK and SYNCH fields can be detected and the identifier of this new header will be recorded. Of course, specific errors on the previous response will be maintained with this identifier reception. ATtiny87/ATtiny167 168 ’ data with the update of the checksum calculation, n 7728G– ...
Page 169
... If no new character has to be sent, LTXOK flag can be cleared separately (see specific flag management described in There is no transmit buffering. No error is detected by this service. 7728G–AVR–06/10 179). 166). 182). Section 15.6.2 on page ATtiny87/ATtiny167 Table 15-1 on page 167. 182). Fig- 169 ...
Page 170
... LIN13 = 0 (default): LIN 2.1 protocol, • LIN13 = 1: LIN 1.3 protocol. The controller checks the LIN13 bit in computing the checksum (enhanced checksum in LIN2.1 / classic checksum in LIN 1.3). This bit is irrelevant for UART commands. ATtiny87/ATtiny167 170 Table Reset of LIN/UART Registers Register Name LIN Control Reg ...
Page 171
... PROTECTED SYNC IDENTIFIER Field Field Node providing neither the master task, neither a slave task LIDOK ATtiny87/ATtiny167 Configuration LIN standard configuration (default) Frame_Time_Out disable Listening mode 8-bit data, no parity & 1 stop-bit 8-bit data, even parity & 1 stop-bit 8-bit data, odd parity & 1 stop-bit ...
Page 172
... BREAK is refused. The re-synchronization is done by adjust- ing LBT[5..0] value to the SYNCH field of the received header (0x55). Then the PROTECTED IDENTIFIER is sampled using the new value of LBT[5..0]. ATtiny87/ATtiny167 172 , the abort command is taken into account at the end of the byte, ...
Page 173
... Write in LINBTR register LENA ? =1 =0 (LINCR bit 4) LDISR to write =0 LBT[5..0] forced to 0x20 LDISR forced to 0 Enable re-synch. in LIN mode ATtiny87/ATtiny167 Figure 15 LBT[5..0] = LBT[5..0] to write (LBT[5..0] =8) min LDISR forced to 1 Disable re-synch. in LIN mode describes how to set or how are automatically 173 ...
Page 174
... The user initializes LTXDL field before setting the Tx Response command, • After setting the Tx Response command, LRXDL is reset by hardware, • LTXDL will remain unchanged during Tx (during busy signal), • LRXDL will count the number of transmitted bytes (during busy signal), ATtiny87/ATtiny167 174 LIDOK st ...
Page 175
... Byte DATA-0 LIN bus 4 0 LRXDL 4 LTXDL LBUSY LCMD=Tx Response Information on response (ex: error on byte) is only available at the end of the serializa- tion/de-serialization of the byte. Section 15.5.13 “Interrupts” on page ATtiny87/ATtiny167 LERR Byte 3 Byte DATA-1 DATA-2 ERROR 1 2 LCMD2..0=000 b 178). ...
Page 176
... After each LIN error, the LIN controller stops its previous activity and returns to its withdrawal mode (LCMD[2..0] = 000 Writing 1 in LERR of LINSIR register resets LERR bit and all the bits of the LINERR register. ATtiny87/ATtiny167 176 178). There are eight flags: 186). A LIN slave application does not distinguish between ...
Page 177
... This calculation is called classic checksum. 7728G–AVR–06/10 T Frame PROTECTED IDENTIFIER DATA-0 Field Field Nominal Bit T Bit T Response_Nominal T Header_Maximum T Response_Maximum T Frame_Maximum n DATA n PROTECTED ID ATtiny87/ATtiny167 > T Frame T Response DATA-n Field Field Maximun T = 1.4 x Header_Nominal T = 1.4 x Response_Nominal Header_Maximum + Response_Maximum n unsigned char DATA n PROTECTED ID. ...
Page 178
... LINERR.3 LINERR.2 LINERR.1 LINERR.0 15.5.14 Message Filtering Message filtering based upon the whole identifier is not implemented. Only a status for frame headers having 0x3C, 0x3D, 0x3E and 0x3F as identifier is available in the LINSIR register. Table 15-4. ATtiny87/ATtiny167 178 n 255 unsigned char DATA = – 0 ...
Page 179
... LINDAT will be for data in. In UART mode the LINSEL register is unused. 15.5.16 OCD Support When a debugger break occurs, the state machine of the LIN/UART controller is stopped (included frame time-out) and further communication may be corrupted. 7728G–AVR–06/10 ATtiny87/ATtiny167 179 ...
Page 180
... R/W 0 LDIV7 LDIV6 LINBRRL 0 R/W 0 — — LINBRRH LTXDL3 LTXDL2 LINDLR 0 R/W 0 LP1 LP0 LINIDR — — LINSEL LDATA7 LDATA6 LINDAT 0 R/W 0 ATtiny87/ATtiny167 180 Bit 5 Bit 4 LCONF1 LCONF0 R/W 0 R/W 0 R/W LIDST0 LBUSY — — LOVERR LFERR LBT5 LBT4 R 1 R/(W) 0 ...
Page 181
... The command is only available if LENA is set. – 000 = LIN Rx Header - LIN abort, – 001 = LIN Tx Header, – 010 = LIN Rx Response, – 011 = LIN Tx Response, – 100 = UART Rx & Tx Byte disable, – 11x = UART Rx Byte enable, – 1x1 = UART Tx Byte enable. ATtiny87/ATtiny167 LCONF0 LENA LCMD2 ...
Page 182
... Bits 7:5 - LIDST[2:0]: Identifier Status • Bit 4 - LBUSY: Busy Signal • Bit 3 - LERR: Error Interrupt enable bit - LENERR - is set in LINENIR. resets all LINERR bits. • Bit 2 - LIDOK: Identifier Interrupt • Bit 1 - LTXOK: Transmit Performed Interrupt LINENIR. ATtiny87/ATtiny167 182 Bit LIDST2 LIDST1 ...
Page 183
... Transmit performed interrupt masked, – Transmit performed interrupt enabled. – Receive performed interrupt masked, – Receive performed interrupt enabled. Bit LABORT LTOERR LOVERR – warning, – LIN abort command occurred. This bit is cleared when LERR bit in LINSIR is cleared. ATtiny87/ATtiny167 LENERR LENIDOK LENTXOK R R/W R/W R ...
Page 184
... Bit 0 - LBERR: Bit Error Flag 15.6.5 LIN Bit Timing Register - LINBTR Read/Write Initial Value • Bit 7 - LDISR: Disable Bit Timing Re synchronization ATtiny87/ATtiny167 184 – error, – Frame_Time_Out error. This bit is cleared when LERR bit in LINSIR is cleared. – error, – Overrun error. ...
Page 185
... In LIN mode, this field gives the number of bytes to be transmitted (clamped to 8 Max). In UART mode this field is unused. In LIN mode, this field gives the number of bytes to be received (clamped to 8 Max). In UART mode this field is unused. ATtiny87/ATtiny167 f clk ) x (LDIV[11.. i/o ...
Page 186
... Bits 5:0 - LID[5:0]: LIN 2.1 Identifier 15.6.9 LIN Data Buffer Selection Register - LINSEL Read/Write Initial Value • Bits 7:4 - Reserved Bits These bits are reserved for future use. For compatibility with future devices, they must be written to zero when LINSEL is written. ATtiny87/ATtiny167 186 Bit LID5 / LP1 ...
Page 187
... In UART mode this field is unused. Bit LDATA7 LDATA6 LDATA5 R/W R/W R LIN mode: FIFO data buffer port. In UART mode: data register (no data buffer - no FIFO). – In Write access, data out. – In Read access, data in. ATtiny87/ATtiny167 LDATA4 LDATA3 LDATA2 LDATA1 R/W R/W R/W R ...
Page 188
... ATtiny87/167 proposes to have an external resistor used in conjunction with the Current Source. The device measures the voltage to the boundaries of the resistance via the Analog to Digital converter. The resulting voltage defines the physical address that the communication handler will use when the node will participate in LIN communication. ATtiny87/ATtiny167 188 AVCC 100 uA ...
Page 189
... Max R 30K load 3V range: Max R 15K load ATtiny87/ATtiny167 Minimum Typical Reading with Reading with a 2.56V ref a 2.56V ref 40 88 132 188 272 1 400 600 880 Minimum Typical Reading with Reading with a 2.56V ref a 2.56V ref ...
Page 190
... Writing this bit to one enables the Current Source as shown in to use DIDR register bit function when ISRCEN is set. It also recommended to turn off the Cur- rent Source as soon as possible ( ex: once the ADC measurement is done). ATtiny87/ATtiny167 190 Table 16-2 (See ”AnaComp - Analog Comparator” on page ...
Page 191
... These options are selected using the REFS[1:0] bits of the ADMUX control register and using AREFEN and XREFEN bits of the AMISCR con- trol register. 7728G–AVR–06/10 ATtiny87/ATtiny167 Figure 191 ...
Page 192
... Figure 17-1. Analog to Digital Converter Block Schematic ATtiny87/ATtiny167 192 8-Bit Data Bus Analog Misc. ADC Multiplexer (AMISCR) Register A & B (ADCSRA/ADCSRB) Select (ADMUX) Internal 2.56 / 1.1V Reference AVCC AGND / AVCC 4 Bandgap Reference Temperature Sensor ADC10 ADC9 ADC8 Pos. AREF ADC7 Input XREF Mux ...
Page 193
... The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the data registers is prohibited between reading of ADCH and ADCL, the inter- rupt will trigger even if the result is lost. 7728G–AVR–06/10 Table 17-5. Table 17-5) is used to measure the voltage to the boundar- ATtiny87/ATtiny167 Table 17-5 to the 193 ...
Page 194
... If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA register to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. ATtiny87/ATtiny167 194 ADTS[2:0] ADIF ADATE SOURCE 1 ...
Page 195
... Three additional CPU clock cycles are used for synchronization logic. In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see 7728G–AVR–06/10 ADEN Reset Start 7-bit ADC Prescaler CLK IO ADPS0 ADPS1 ADPS2 ATtiny87/ATtiny167 Table 17-1. 195 ...
Page 196
... Figure 17-5. ADC Timing Diagram, Single Conversion ycle Number DC Clock DSC DIF DCH DCL Figure 17-6. ADC Timing Diagram, Auto Triggered Conversion ycle Number DC Clock igger ource DATE DIF DCH DCL ATtiny87/ATtiny167 196 MUX and REFS Sample & Hold Update One Conversion ...
Page 197
... Sample & Hold (Cycles from Start of Conversion) a. When ADATE or ADEN is cleared. b. During conversion, minimum one ADC clock cycle after the trigger event. c. After a conversion, before the Interrupt Flag used as trigger source is cleared. ATtiny87/ATtiny167 Conversion Time (Cycles) 13.5 cycles 1.5 cycles 2 cycles 13 ...
Page 198
... ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path). ATtiny87/ATtiny167 198 REF will result in codes close to 0x3FF. V REF a ...
Page 199
... Use the ADC noise canceler function to reduce induced noise from the CPU any port pins are used as digital outputs essential that these do not switch while a conversion is in progress. ATtiny87/ATtiny167 /2) should not be present to avoid ADC 1..100 kO C ...
Page 200
... Ideal value: 0 LSB Figure 17-10. Gain Error • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. ATtiny87/ATtiny167 200 Output Code Offset Error ...