ADUC812BS Analog Devices Inc, ADUC812BS Datasheet
ADUC812BS
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ADUC812BS Summary of contents
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FEATURES Analog I/O 8-Channel, High Accuracy 12-Bit ADC On-Chip, 100 ppm/ C Voltage Reference High Speed 200 kSPS DMA Controller for High Speed ADC-to-RAM Capture 2 12-Bit Voltage Output DACs On-Chip Temperature Sensor Function Memory 8K Bytes On-Chip Flash/EE ...
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ADuC812 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Differential Nonlinearity Offset Error Full-Scale Error Full-Scale Mismatch ANALOG OUTPUTS Voltage Range_0 Voltage Range_1 Resistive Load Capacitive Load Output Impedance I SINK REV 5.0 V 10%, REF 100 pF. All specifications ADuC812BS ±1/2 ±1/2 ±1.5 ±1.5 ±1.5 ±1.5 ±1 ± ±5 ±5 ±1 ± ± ...
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... INH XTAL1 Input High Voltage (V ) Only INH Input Low Voltage (V ) INL Input Leakage Current (Port 0, EA) Logic 1 Input Current (All Digital Inputs) Logic 0 Input Current (Port Logic 1-0 Transition Current (Port –700 Input Capacitance ADuC812BS Unit µs typ sec typ 2.3/V 2 ...
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... Typical specifications are not production tested, but are supported by characterization data at initial product release. Timing Specifications—See Pages 46–55. Specifications subject to change without notice. Please refer to User Guide, Quick Reference Guide, Application Notes, and Silicon Errata Sheet at www.analog.com/microconverter for additional information. REV. E ADuC812BS ...
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... P1.6/ADC6 Model ADuC812BS ADuC812BS EVAL-ADuC812QS EVAL-ADuC812QSP CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADuC812 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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Mnemonic Type Function DV P Digital Positive Supply Voltage Nominal Analog Positive Supply Voltage Nominal Decoupling Input for On-Chip Reference. Connect 0.1 µF between ...
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ADuC812 Mnemonic Type Function PSEN O Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations active every six oscillator periods except during external ...
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ARCHITECTURE, MAIN FEATURES The ADuC812 is a highly integrated, true 12-bit data acquisi- tion system. At its core, the ADuC812 incorporates a high performance 8-bit (8052 compatible) MCU with on-chip reprogrammable nonvolatile Flash program memory control- ling a multichannel (eight ...
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ADuC812 OVERVIEW OF MCU-RELATED SFRs Accumulator SFR ACC is the Accumulator register and is used for math opera- tions including addition, subtraction, integer multiplication and division, and Boolean bit manipulations. The mnemonics for accumulator-specific instructions refer to the Accumulator as ...
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SPECIAL FUNCTION REGISTERS All registers except the program counter and the four general-purpose register banks reside in the special function register (SFR) area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and ...
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ADuC812 ADC CIRCUIT INFORMATION General Overview The ADC conversion block incorporates a fast, 8-channel, 12-bit, single-supply ADC. This block provides the user with multichannel mux, track-and-hold, on-chip reference, calibra- tion features, and ADC. All components in this block are easily ...
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ADCCON1—(ADC Control SFR #1) The ADCCON1 register controls conversion and acquisition times, hardware conversion modes and power-down modes as detailed below. SFR Address EFH SFR Power-On Default Value 20H Bit Name Description ...
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ADuC812 ADCCON2—(ADC Control SFR #2) The ADCCON2 register controls ADC channel selection and conversion modes as detailed below. SFR Address D8H SFR Power-On Default Value 00H ocation Name Description L ADCCON2.7 ...
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Driving the ADC The ADC incorporates a successive approximation (SAR) archi- tecture involving a charge-sampled input stage. Figure 7 shows the equivalent circuit of the analog input section. Each ADC conversion is divided into two distinct phases as defined by ...
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ADuC812 However, be sure to include the Schottky diodes shown in Figure 8 (or at least the lower of the two diodes) to protect the analog input from undervoltage conditions. To summarize this section, use the circuit of Figure 8 ...
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ADuC812 core. This mode allows the ADuC812 to capture a contiguous sample stream at full ADC update rates (200 kHz). DMA Mode Configuration Example To set the ADuC812 into DMA mode, a number of steps ...
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ADuC812 and the gain calibration coefficient is divided into ADCGAINH (six bits) and ADCGAINL (eight bits). The offset calibration coefficient compensates for dc offset errors in both the ADC and the input signal. Increasing the offset coefficient compensates for positive ...
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Using the Flash/EE Program Memory This 8K byte Flash/EE program memory array is mapped into the lower 8K bytes of the 64K bytes program space address- able by the ADuC812 and will be used to hold user code in typical ...
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ADuC812 ECON—Flash/EE Memory Control SFR This SFR acts as a command interpreter and may be written with one of five command modes to enable various read, pro- gram, and erase cycles as detailed in Table VII. Table VII. ECON—Flash/EE Memory ...
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USER INTERFACE TO OTHER ON-CHIP ADuC812 PERIPHERALS The following section gives a brief overview of the various peripherals also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given. DAC The ADuC812 incorporates ...
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ADuC812 Using the DAC The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier, the functional equivalent of which is illustrated in Figure 18. Details of the actual DAC architecture can be found in ...
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SOURCE/SINK CURRENT – mA Figure 21. Source and Sink Current Capability with REF DD To drive significant loads with the DAC outputs, external buffering may be required, as ...
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ADuC812 WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset within a reasonable amount of time if the ADuC812 enters an erroneous state, possibly due to a programming error. The Watch- dog function can be ...
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Power Supply Monitor PSMCON Control Register SFR Address DFH Power-On Default Value DCH Bit Addressable No — Bit Name Description 7 — Not Used. 6 CMP AV This is a read-only bit and directly reflects the ...
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ADuC812 MOSI (Master Out, Slave In Pin) The MOSI (master out, slave in) pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on the master (data out) should be ...
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SPIDAT SPI Data Register Function The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read data just received by the SPI interface. SFR Address F7H Power-On Default Value ...
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ADuC812 COMPATIBLE INTERFACE The ADuC812 supports a 2-wire serial interface mode that compatible. The I C compatible interface shares its pins with the on-chip SPI interface and therefore the user can only ...
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COMPATIBLE ON-CHIP PERIPHERALS This section gives a brief overview of the various secondary peripheral circuits that are also available to the user on-chip. These remaining functions are fully 8051 compatible and are controlled via standard 8051 SFR bit definitions. ...
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ADuC812 User configuration and control of all Timer operating modes is achieved via three SFRs: TMOD, TCON Control and configuration for Timers 0 and 1. T2CON Control and configuration for Timer 2. Timer/Counter 0 and TMOD 1 Mode Register SFR ...
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Timer/Counter 0 and TCON 1 Control Register SFR Address 88H Power-On Default Value 00H Bit Addressable Yes *These bits are not used in the control of Timer/Counter 0 and 1, but are used ...
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ADuC812 TIMER/COUNTERS 0 AND 1 OPERATING MODES The following paragraphs describe the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for Timer 0 as for Timer ...
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Timer/Counter 2 T2CON Control Register SFR Address C8H Power-On Default Value 00H Bit Addressable Yes Bit Name Description 7 TF2 Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. ...
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ADuC812 Timer/Counter Operation Modes The following paragraphs describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table XVIII. Table XVIII. TIMECON SFR Bit Designations RCLK (or) TCLK CAP2 ...
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UART SERIAL INTERFACE The serial port is full-duplex, meaning it can transmit and receive simultaneously also receive-buffered, meaning it can begin receiving a second byte before a previously received byte has been read from the receive register. However, ...
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ADuC812 Mode 0 (8-Bit Shift Register Mode) Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RxD. TxD outputs the shift clock. Eight data bits are transmitted ...
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Timer 1 Generated Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: Modes and ...
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ADuC812 INTERRUPT SYSTEM The ADuC812 provides a total of nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt related SFRs. IE Interrupt Enable Register IP Interrupt Priority Register ...
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Secondary Interrupt IE2 Enable Register SFR Address A9H Power-On Default Value 00H Bit Addressable No — — — Bit Name Description 7 — Reserved for future use. 6 — Reserved for future use. 5 — Reserved for future use. 4 ...
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ADuC812 ADuC812 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design consider- ations that must be addressed when integrating the ADuC812 into any hardware system. Clock Oscillator The clock source for the ADuC812 can come either from ...
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If access to more than 64K bytes of RAM is desired, a feature unique to the ADuC812 allows addressing MBytes of external RAM simply by adding an additional latch as illus- trated in Figure 39. ADuC812 P0 ...
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ADuC812 As an alternative to providing two separate power supplies, the user can help keep AV quiet by placing a small series resistor DD and/or ferrite bead between it and separately to ground. An example of this ...
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Grounding and Board Layout Recommendations As with all high resolution data converters, special attention must be paid to grounding and PC board layout of ADuC812 based designs in order to achieve optimum performance from the ADC and DACs. Although the ...
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ADuC812 ANALOG INPUT V OUTPUT REF DAC OUTPUT DV DD ADM810 V CC GND OTHER HARDWARE CONSIDERATIONS To facilitate in-circuit programming, plus in-circuit debug and emulation options, users will want to implement some simple connection points in their hardware that ...
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Note that the serial port debugger is fully contained on the ADuC812 device, (unlike ROM monitor type debuggers) and therefore no external memory is needed to enable in-system debug sessions. Single-Pin Emulation Mode Also built into the ADuC812 is a ...
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ADuC812 TIMING SPECIFICATIONS Parameter CLOCK INPUT (External Clock Driven XTAL1) t XTAL1 Period CK t XTAL1 Width Low CKL t XTAL1 Width High CKH t XTAL1 Rise Time CKR t XTAL1 Fall Time CKF 4 t ADuC812 ...
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Parameter EXTERNAL PROGRAM MEMORY READ CYCLE t ALE Pulsewidth LHLL t Address Valid to ALE Low AVLL t Address Hold after ALE Low LLAX t ALE Low to Valid Instruction In LLIV ALE Low to PSEN Low t LLPL PSEN ...
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ADuC812 Parameter EXTERNAL DATA MEMORY READ CYCLE RD Pulsewidth t RLRH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX RD Low to Valid Data In t RLDV Data and Address Hold after RD t ...
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Parameter EXTERNAL DATA MEMORY WRITE CYCLE WR Pulsewidth t WLWH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX ALE Low Low t LLWL Address Valid Low ...
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ADuC812 Parameter UART TIMING (Shift Register Mode) t Serial Port Clock Cycle Time XLXL t Output Data Setup to Clock QVXH t Input Data Setup to Clock DVXH t Input Data Hold after Clock XHDX t Output Data Hold after ...
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Parameter COMPATIBLE INTERFACE TIMING t SCLOCK Low Pulsewidth LOW t SCLOCK High Pulsewidth HIGH t Start Condition Hold Time HD; STA t Data Setup Time SU; DAT t Data Hold time HD; DAT t Setup time for ...
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ADuC812 Parameter SPI MASTER MODE TIMING (CPHA = 1) t SCLOCK Low Pulsewidth LOW t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold ...
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Parameter SPI MASTER MODE TIMING (CPHA = 0) t SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Output Setup before SCLOCK Edge DOSU t Data Input Setup Time before ...
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ADuC812 Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK ...
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Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge ...
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ADuC812 1.03 0.88 0.73 SEATING PLANE VIEW A 0.23 0.11 BSC SQ PIN 1 INDICATOR 1.00 12 MAX 0.90 0.80 0.20 REF SEATING PLANE OUTLINE DIMENSIONS 52-Lead Metric Quad Flat Package [MQFP] (S-52) Dimensions shown in millimeters 14.15 13.90 SQ ...
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Revision History Location 4/03—Data Sheet changed from REV REV. E. Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . ...
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