ADUC824BS Analog Devices Inc, ADUC824BS Datasheet

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GENERAL DESCRIPTION The ADuC824 is a complete smart transducer front-end, inte- grating two high-resolution sigma delta ADCs, an 8-bit MCU, and program/data Flash/EE Memory on a single chip. This low power device accepts low-level signals directly from a transducer. ...

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ADuC824 TABLE OF CONTENTS FEATURES .......................................................................... 1 GENERAL DESCRIPTION ................................................. 1 SPECIFICATIONS .............................................................. 3 TIMING SPECIFICATIONS .............................................. 8 ABSOLUTE MAXIMUM RATINGS ................................. 18 PIN CONFIGURATION .................................................... 18 ORDERING GUIDE .......................................................... 18 PIN FUNCTION DESCRIPTIONS................................... 19 ADuC824 BLOCK DIAGRAM .......................................... 21 ...

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... Relative Accuracy Differential Nonlinearity Offset Error 8 Gain Error Specifications Voltage Output Settling Time Digital-to-Analog Glitch Energy = ADuC824BS Test Conditions/Comments 5.4 On Both Channels 105 Programmable in 0.732 ms Increments Update Rate Range = ± Update Rate 13 Range = ± 2. Update Rate 18 See Tables IX and X Output Noise Varies with Selected ...

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... ANALOG (DAC) OUTPUTS Voltage Range Resistive Load Capacitive Load Output Impedance I SINK TEMPERATURE SENSOR Accuracy Thermal Impedance (θ ADuC824BS Test Conditions/Comments 1.25 ± 1% Initial Tolerance @ 25° 100 2.5 ± 1% Initial Tolerance @ 25° ± 100 External Reference Voltage = 2.5 V RN2, RN1, RN0 of ADC0CON Set to ± ...

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... Logic Inputs, XTAL1 Only V , Input Low Voltage INL V , Input High Voltage INH XTAL1 Input Capacitance XTAL2 Output Capacitance ADuC824BS Test Conditions/Comments –100 AIN+ is the Selected Positive Input to the Primary ADC +100 AIN– is the Selected Negative Input to the Auxiliary ADC ± 10 0.03 – ...

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... After WDT Reset in Normal Mode FLASH/EE MEMORY RELIABILITY CHARACTERISTICS 15 Endurance 16 Data Retention POWER REQUIREMENTS Power Supply Voltages Nominal Operation Nominal Operation Nominal Operation Nominal Operation DD ADuC824BS Test Conditions/Comments 2 2 SOURCE 2 SOURCE 0 mA, SCLOCK, SDATA/MOSI V max SINK 0 mA, P1.0 and P1.1 SINK ...

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... PLLCON, PCON Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in PLLCON SFR power supply current will increase typically operation) and operation) during a Flash/EE memory program or erase cycle. DD Specifications subject to change without notice. ADuC824BS Test Conditions/Comments 17 4. 5.25 V, Core CLK = 1.57 MHz DD 2 ...

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ADuC824 TIMING SPECIFICATIONS Parameter CLOCK INPUT (External Clock Driven XTAL1) t XTAL1 Period CK t XTAL1 Width Low CKL t XTAL1 Width High CKH t XTAL1 Rise Time CKR t XTAL1 Fall Time CKF 1/t ADuC824 Core ...

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Parameter EXTERNAL PROGRAM MEMORY t ALE Pulsewidth LHLL t Address Valid to ALE Low AVLL t Address Hold after ALE Low LLAX t ALE Low to Valid Instruction In LLIV ALE Low to PSEN Low t LLPL PSEN Pulsewidth t ...

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ADuC824 Parameter EXTERNAL DATA MEMORY READ CYCLE RD Pulsewidth t RLRH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX RD Low to Valid Data In t RLDV Data and Address Hold after RD t ...

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Parameter EXTERNAL DATA MEMORY WRITE CYCLE WR Pulsewidth t WLWH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX ALE Low to WR Low t LLWL Address Valid to WR Low t AVWL Data Valid ...

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ADuC824 Parameter UART TIMING (Shift Register Mode) t Serial Port Clock Cycle Time XLXL t Output Data Setup to Clock QVXH t Input Data Setup to Clock DVXH t Input Data Hold after Clock XHDX t Output Data Hold after ...

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Parameter 2 I C-COMPATIBLE INTERFACE TIMING t SCLOCK Low Pulsewidth L t SCLOCK High Pulsewidth H t Start Condition Hold Time SHD t Data Setup Time DSU t Data Hold Time DHD t Setup Time for Repeated Start RSU t ...

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ADuC824 Parameter SPI MASTER MODE TIMING (CPHA = 1) t SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold ...

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Parameter SPI MASTER MODE TIMING (CPHA = 0) t SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Output Setup before SCLOCK Edge DOSU t Data Input Setup Time before ...

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ADuC824 Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK ...

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Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge ...

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... ADuC824 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Windows is a registered trademark of Microsoft Corporation. Temperature Model Range ADuC824BS –40°C to +85°C + 0.3 V QuickStart DD + 0.3 V Development ...

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Pin No. Mnemonic Type Description 1 P1.0/T2 I/O Port 1.0 can function as a digital input or digital output and has a pull-up configuration as described below for Port 3. P1.0 has an increased current drive sink capability of 10 ...

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ADuC824 Pin No. Mnemonic Type Description 22–25 P3.4–P3.7 I/O P3.4–P3.7 are bidirectional port pins with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can ...

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AIN1 AIN BUF PGA AIN2 MUX AIN3 AUXILIARY ADC AIN AIN4 16-BIT MUX - ADC AIN5 BANDGAP TEMP REFERENCE SENSOR REFIN V REF REFIN DETECT 200 A 200 A ...

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ADuC824 MEMORY ORGANIZATION As with all 8051-compatible devices, the ADuC824 has sepa- rate address spaces for Program and Data memory as shown in Figure 13 and Figure 14. If the user applies power or resets the device while the EA ...

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The SFR space is mapped to the upper 128 bytes of internal data memory space and accessed by direct addressing only. It provides an interface between the CPU and all on-chip peripherals. A block diagram showing the programming model of ...

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ADuC824 SPECIAL FUNCTION REGISTERS All registers, except the program counter and the four general- purpose register banks, reside in the SFR area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and all ...

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SFR INTERFACE TO THE PRIMARY AND AUXILIARY ADCS Both ADCs are controlled and configured via a number of SFRs that are mentioned here and described in more detail in the following pages. ADCSTAT: ADC Status Register. Holds general status of ...

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ADuC824 ADCMODE (ADC Mode Register) Used to control the operational mode of both ADCs. SFR Address D1H Power-On Default Value 00H Bit Addressable No — — Bit Name Description 7 — Reserved for Future Use 6 — Reserved ...

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ADC0CON (Primary ADC Control Register) Used to configure the Primary ADC for range, channel selection, external Ref enable, and unipolar or bipolar coding. SFR Address D2H Power-On Default Value 07H Bit Addressable No — Bit ...

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ADuC824 ADC1CON (Auxiliary ADC Control Register) Used to configure the Auxiliary ADC for channel selection, external Ref enable and unipolar or bipolar coding. It should be noted that the Auxiliary ADC only operates on a fixed input range of ± ...

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ICON (Current Sources Control Register) Used to control and configure the various excitation and burnout current source options available on-chip. SFR Address D5H Power-On Default Value 00H Bit Addressable No — Bit Name Description 7 — ...

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ADuC824 OF0H/OF0M/OF0L (Primary ADC Offset Calibration Registers ) These three 8-bit registers hold the 24-bit offset calibration coefficient for the Primary ADC. These registers are configured at power- on with a factory default value of 800000Hex. However, these bytes will ...

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PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION Overview The ADuC824 incorporates two independent sigma-delta ADCs (Primary and Auxiliary) with on-chip digital filtering intended for the measurement of wide dynamic range, low frequency signals, such as those in weigh-scale, strain-gauge, pressure trans- ...

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ADuC824 Auxiliary ADC The Auxiliary ADC is intended to convert supplementary inputs such as those from a cold junction diode or thermistor. This ADC is not buffered and has a fixed input range 2.5 V THE ...

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PRIMARY AND AUXILIARY ADC NOISE PERFORMANCE Tables IX, X, and XI below show the output rms noise in µV and output peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB) for some typical output update rates on both the ...

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ADuC824 The absolute input voltage range on the auxiliary ADC is restricted to between AGND – AVDD + 30 mV. The slightly negative absolute input voltage limit does allow the possibility of monitoring small signal bipolar signals ...

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Excitation Currents The ADuC824 also contains two identical 200 µA constant current sources. Both source current from AVDD to Pin #3 (IEXC1) or Pin #4 (IEXC2). These current sources are con- trolled via bits in the ICON SFR shown in ...

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ADuC824 Figure 22 shows the frequency response of the ADC chan- nel at the default SF word of 69 dec or 45 hex, yielding an overall output update rate of just under 20 Hz. It should be noted that this ...

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Calibration The ADuC824 provides four calibration modes that can be pro- grammed via the mode bits in the ADCMODE SFR detailed in Table IV. In fact, every ADuC824 has already been factory calibrated. The resultant Offset and Gain calibration coefficients ...

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ADuC824 Endurance quantifies the ability of the Flash/EE memory to be cycled through many Program, Read, and Erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events. These events are defined as: a. initial ...

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Table XII. Flash/EE Memory Parallel Programming Modes Port 3 Pins 0.7 0.6 0.5 0.4 0.3 0.2 0 ...

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ADuC824 ECON—Flash/EE Memory Control SFR This SFR acts as a command interpreter and may be written with one of five command modes to enable various read, program and erase cycles as detailed in Table XIII. Table XIII. ECON–Flash/EE Memory Control ...

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USER INTERFACE TO OTHER ON-CHIP ADuC824 PERIPHERALS The following section gives a brief overview of the various peripher- als also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given. DAC The ADuC824 ...

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ADuC824 ON-CHIP PLL The ADuC824 is intended for use with a 32.768 kHz watch crys- tal. A PLL locks onto a multiple (384) of this to provide a stable 12.582912 MHz clock for the system. The core can operate at ...

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TIME INTERVAL COUNTER (TIC) A time interval counter is provided on-chip for counting longer intervals than the standard 8051-compatible timers are capable of. The TIC is capable of timeout intervals ranging from 1/128th second to 255 hours. Furthermore, this counter ...

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ADuC824 TIMECON TIC Control Register SFR Address A1H Power-On Default Value 00H Bit Addressable No — — Bit Name Description 7 — Reserved for Future Use 6 — Reserved for Future Use. For future product code compatibility this bit should ...

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INTVAL User Time Interval Select Register Function User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) bit is ...

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ADuC824 WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC824 enters an erroneous state, possibly due to a programming error, electrical noise, or RFI. ...

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POWER SUPPLY MONITOR As its name suggests, the Power Supply Monitor, once enabled, monitors both supplies (AVDD or DVDD) on the ADuC824. It will indicate when any of the supply pins drop below one of four user-selectable voltage trip points ...

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ADuC824 SERIAL PERIPHERAL INTERFACE The ADuC824 integrates a complete hardware Serial Peripheral Interface (SPI) interface on-chip. SPI is an industry standard syn- chronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full ...

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SPIDAT SPI Data Register Function The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read data just received by the SPI interface. SFR Address F7H Power-On Default Value ...

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ADuC824 2 I C-COMPATIBLE INTERFACE The ADuC824 supports a 2-wire serial interface mode which compatible. The I C-compatible interface shares its pins with the on-chip SPI interface and therefore the user can only enable one ...

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ON-CHIP PERIPHERALS This section gives a brief overview of the various secondary periph- eral circuits are also available to the user on-chip. These remaining functions are fully 8051-compatible and are controlled via standard 8051 SFR bit definitions. Parallel I/O ...

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ADuC824 User configuration and control of all Timer operating modes is achieved via three SFRs namely: TMOD, TCON: Control and configuration for Timers 0 and 1. T2CON: Control and configuration for Timer 2. TMOD Timer/Counter 0 and 1 Mode Register ...

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TCON Timer/Counter 0 and 1 Control Register SFR Address 88H Power-On Default Value 00H Bit Addressable Yes These bits are not used in the control of timer/counter 0 and 1, but are used instead ...

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ADuC824 TIMER/COUNTER 0 AND 1 OPERATING MODES The following paragraphs describe the operating modes for timer/ counters 0 and 1. Unless otherwise noted, assume that these modes of operation are the same for timer 0 as for timer 1. Mode ...

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T2CON Timer/Counter 2 Control Register SFR Address C8H Power-On Default Value 00H Bit Addressable Yes Bit Name Description 7 TF2 Timer 2 Overflow Flag Set by hardware on a Timer 2 overflow. ...

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ADuC824 Timer/Counter 2 Operating Modes The following paragraphs describe the operating modes for timer/ counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table XXVI. Table XXVI. TIMECON SFR Bit Designations RCLK (or) ...

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UART SERIAL INTERFACE The serial port is full duplex, meaning it can transmit and receive simultaneously also receive-buffered, meaning it can com- mence reception of a second byte before a previously received byte has been read from the ...

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ADuC824 Mode 0: 8-Bit Shift Register Mode Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted ...

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Timer 1 Generated Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: /32) × ...

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ADuC824 INTERRUPT SYSTEM The ADuC824 provides a total of twelve interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three Interrupt-related SFRs. IE: Interrupt Enable Register. IP: Interrupt Priority Register. IEIP2: ...

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IEIP2 Secondary Interrupt Enable and Priority Register SFR Address A9H Power-On Default Value A0H Bit Addressable No — Bit Name Description 7 — Reserved for Future Use 6 PTI Written by User to Select TIC Interrupt ...

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ADuC824 ADuC824 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design consider- ations that must be addressed when integrating the ADuC824 into any hardware system. Clock Oscillator As described earlier, the core clock frequency for the ADuC824 ...

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ADuC824 P0 LATCH ALE P2 LATCH either implementation, Port 0 (P0) serves as a multiplexed address/data bus. It emits the low byte of the data pointer (DPL address, which is latched by a pulse of ...

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ADuC824 As an alternative to providing two separate power supplies, AV quiet by placing a small series resistor and/or ferrite bead between it and DV , and then decoupling example of this configuration is shown in Figure ...

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PLACE ANALOG A COMPONENTS HERE AGND PLACE ANALOG B COMPONENTS HERE AGND PLACE ANALOG C COMPONENTS HERE GND In all of these scenarios, and in more complicated real-life appli- cations, keep in mind the flow of current from the supplies ...

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ADuC824 AV DD 200 A/400 A EXCITATION CURRENT V + REF R1 V – 5.6k REF RTD A – 510 DV DD ADM810 V RST CC GND C1+ V+ C1– C2+ C2– V– T2OUT R2IN ...

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QUICKSTART DEVELOPMENT SYSTEM The QuickStart Development System is a full featured, low cost development tool suite supporting the ADuC824. The system consists of the following PC-based (Windows-compatible) hard- ware and software development tools. Hardware: ADuC824 Evaluation Board, Plug-In Power Supply ...

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ADuC824 CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Revision History Location 5/02—Data Sheet changed from REV REV. B. Edits to SPECIFICATIONS ...