EP7312-CV-90 Cirrus Logic Inc, EP7312-CV-90 Datasheet
EP7312-CV-90
Specifications of EP7312-CV-90
Available stocks
Related parts for EP7312-CV-90
EP7312-CV-90 Summary of contents
Page 1
... tro lle r SRAM I/F SDRAM I/F MEMORY and STORAGE © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7312 Data Sheet High-performance, with SDRAM & Enhanced Digital Audio Interface ™ EP7312 is designed for ultra-low-power ® & rru p ts & & I/F ...
Page 2
... LQFP ® Support — 256-Ball PBGA — 204-Ball TFBGA ❑ The fully static EP7312 is optimized for low power dissipation and is fabricated using a 0.25 micron CMOS process. The EP7312 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters ...
Page 3
... Table of Contents FEATURES ...........................................................................................................................................1 OVERVIEW ...........................................................................................................................................1 Description of the EP7312’s Components, Functionality, and Interfaces ....................................6 Processor Core - ARM720T ..................................................................................................................................6 Power Management ..............................................................................................................................................6 MaverickKey™ Unique ID ......................................................................................................................................6 Memory Interfaces .................................................................................................................................................6 Digital Audio Capability .........................................................................................................................................7 Universal Asynchronous Receiver/Transmitters (UARTs) .....................................................................................7 Digital Audio Interface (DAI) ..................................................................................................................................7 CODEC Interface ..................................................................................................................................................8 SSI2 Interface ........................................................................................................................................................8 Synchronous Serial Interface ................................................................................................................................8 LCD Controller ...
Page 4
... High-Performance, Low-Power System on Chip Packages ............................................................................................................................................ 30 208-Pin LQFP Package Characteristics ............................................................................................................. 30 EP7312 208-Pin LQFP ............................................................................................................................ 30 208-Pin LQFP Pin Diagram ................................................................................................................................ 31 EP7312 ............................................................................................................................................... 31 208-Pin LQFP Numeric Pin Listing ..................................................................................................................... 32 204-Ball TFBGA Package Characteristics .......................................................................................................... 38 204-Ball TFBGA Pinout (Top View) ..................................................................................................................... 39 204-Ball TFBGA Ball Listing ............................................................................................................................... 40 256-Ball PBGA Package Characteristics ............................................................................................................ 46 256-Ball PBGA Pinout (Top View) ....................................................................................................................... 48 256-Ball PBGA Ball Listing ...
Page 5
... List of Figures Figure 1. A Fully-Configured EP7312-Based System ...................................................................................................12 Figure 2. Legend for Timing Diagrams .........................................................................................................................15 Figure 3. SDRAM Load Mode Register Cycle Timing Measurement ............................................................................17 Figure 4. SDRAM Burst Read Cycle Timing Measurement ..........................................................................................18 Figure 5. SDRAM Burst Write Cycle Timing Measurement ..........................................................................................19 Figure 6. SDRAM Refresh Cycle Timing Measurement ................................................................................................20 Figure 7. Static Memory Single Read Cycle Timing Measurement ...............................................................................22 Figure 8 ...
Page 6
... Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP7312 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP7312 is powering, and then deliver the copyrighted information over a secure connection ...
Page 7
... RISC processor, and the availability of efficient C-compilers and other software development tools, ensures that a wide range of audio decompression algorithms can easily be ported to and run on the EP7312 Universal Asynchronous Receiver/Transmitters (UARTs) The EP7312 includes two 16550-type UARTs for RS-232 serial communications, both of which have two 16-byte FIFOs for receiving and transmitting data ...
Page 8
... CL2 DD[3:0] FRM M 64-Key Keypad Interface Matrix keyboards and keypads can be easily read by the EP7312. A dedicated 8-bit column driver output generates © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) shows the Synchronous Serial Interface pin Table 8. Serial Interface Pin Assignments ...
Page 9
... Pins are multiplexed. See Table 19 on page 11 more information. DS508F1 Real-Time Clock The EP7312 contains a 32-bit Real Time Clock (RTC) that can be written to and read from in the same manner as the timer counters. It also contains a 32-bit output match register which can be programmed to generate an interrupt. • ...
Page 10
... The internal 128-byte Boot ROM facilitates download of saved GPIO port E code to the on-board SRAM/FLASH. GPIO port E Packaging for The EP7312 is available in a 208-pin LQFP package, 256-ball PBGA package 204-ball TFBGA package. ® support © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) ...
Page 11
... CODEC. The selection between SSI2 and the CODEC is controlled by the state of the SERSEL bit in SYSCON2. The choice between the SSI2, CODEC, and the DAI is controlled by the DAISEL bit in SYSCON3 (see the EP7312 User’s Manual for more information). Table 18. DAI/SSI2/CODEC Pin Multiplexing ...
Page 12
... EP7312 High-Performance, Low-Power System on Chip System Design As shown in system block diagram, simply adding desired memory and peripherals to the highly integrated EP7312 CRYSTAL CRYSTAL ×16 SDRAM SDRAM ×16 SDRAM SDRAM ×16 FLASH FLASH ×16 FLASH FLASH EXTERNAL MEMORY- BUFFERS MAPPED EXPANSION BUFFERS ...
Page 13
... 100 10.0 © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7312 Unit Conditions DDIO DDIO VIL to VIH V IOH = 0 IOH = IOH = IOL = –0 IOL = – IOL = –12 mA VIN = V or GND µA DD VOUT = V or GND µ ...
Page 14
... EP7312 High-Performance, Low-Power System on Chip Symbol Parameter CI/O Transceiver capacitance Standby current consumption IDD STANDBY Core, Osc, RTC @2 I/O @ 3.3 V Standby current consumption IDD STANDBY Core, Osc, RTC @2 I/O @ 3.3 V Standby current consumption IDD STANDBY Core, Osc, RTC @2 I Idle current consumption ...
Page 15
... Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are specified 3.1 - 3.5 V and over an operating temperature of -40°C to +85°C. Pin loadings is 50 pF. The timing values are DDIO SS referenced to 1 DS508F1 High-Performance, Low-Power System on Chip Figure 2. Legend for Timing Diagrams © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7312 15 ...
Page 16
... EP7312 High-Performance, Low-Power System on Chip SDRAM Interface Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the values for the timings of each of the SDRAM modes. Parameter SDCLK falling edge to SDCS assert delay time SDCLK falling edge to SDCS deassert delay time ...
Page 17
... The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading. Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal DS508F1 High-Performance, Low-Power System on Chip t CSd t RAd t CAd t ADx t MWd © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7312 17 ...
Page 18
... EP7312 High-Performance, Low-Power System on Chip SDRAM Burst Read Cycle SDCLK t CSa t SDCS CSd t RAa t SDRAS RAd SDCAS t ADv ADRAS ADDR DATA SDQM [0:3] SDMWE Note: 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading. ...
Page 19
... High-Performance, Low-Power System on Chip t t CSa CSa t t CSd CSd t RAd t CAa t CAd t t ADv ADv ADRAS t t DAd DAd MWa Figure 5. SDRAM Burst Write Cycle Timing Measurement © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7312 ADCAS t t DAd DAd MWd 19 ...
Page 20
... EP7312 High-Performance, Low-Power System on Chip SDRAM Refresh Cycle SDCLK SDCS SDRAS SDCAS SDATA ADDR SDQM [3:0] SDMWE Note: 1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading. ...
Page 21
... EXPREADY setup to EXPCLK falling edge time EXPCLK falling edge to EXPREADY hold time DS508F1 High-Performance, Low-Power System on Chip Symbol t CSd t CSh MWd t MWh t MOEd t MOEh t HWd t WDd Dnv WRd t EXs t EXh © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7312 Min Typ Max Unit ...
Page 22
... EP7312 High-Performance, Low-Power System on Chip Static Memory Single Read Cycle EXPCLK t CSd nCS nMWE nMOE t HWd HALF- WORD t WDd WORD D EXPRDY t WRd WRITE Figure 7. Static Memory Single Read Cycle Timing Measurement Note: 1. The cycle time can be extended by integer multiples of the clock period ( MHz MHz ...
Page 23
... Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with valid timing under zero wait state conditions. 3. Address, Data, Halfword, Word, and Write hold state until next cycle. DS508F1 t CSd MWd MWh EXs EXh © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip t CSh EP7312 23 ...
Page 24
... EP7312 High-Performance, Low-Power System on Chip Static Memory Burst Read Cycle EXPCLK t CSd nCS nMWE t MOEd nMOE t HWd HALF WORD t WORD WDd D EXPRDY t WRd WRITE Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive cycles that can be driven ...
Page 25
... Address, Data, Halfword, Word, and Write hold state until next cycle. DS508F1 MWd t t MWh MWh Dnv Dv Dnv t EXh Figure 10. Static Memory Burst Write Cycle Timing Measurement © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip MWd MWd t MWh Dnv Dv EP7312 t CSh t MWh 25 ...
Page 26
... EP7312 High-Performance, Low-Power System on Chip SSI1 Interface Parameter ADCCLK falling edge to nADCCSS deassert delay time ADCIN data setup to ADCCLK rising edge time ADCIN data hold from ADCCLK rising edge time ADCCLK falling edge to data valid delay time ADCCLK falling edge to data invalid delay time ...
Page 27
... Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip Symbol Min Max t 185 2050 clk_per t 925 1025 clk_high t 925 1025 clk_low clkrf FRd FRa t 960 990 FR_per RXs RXh TXd t 960 990 TXv t clk_high clk_low EP7312 Unit ...
Page 28
... EP7312 High-Performance, Low-Power System on Chip LCD Interface Parameter CL[2] falling to CL[1] rising delay time CL[1] falling to CL[2] rising delay time CL[1] falling to FRM transition time CL[1] falling to M transition time CL[2] rising to DD (display data) transition time CL[2] t CL1d CL[1] FRM ...
Page 29
... TCK TMS TDI t JPzx TDO DS508F1 High-Performance, Low-Power System on Chip Symbol t clk_per t clk_high t clk_low t JPs t JPh t JPco t JPzx t JPxz t JPh t JPs t JPco Figure 14. JTAG Timing Measurement © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7312 Min Max Units JPxz 29 ...
Page 30
... Pin 1 Indicator 1.35 (0.053) 0.45 (0.018) 1.45 (0.057) 0.75 (0.030) Figure 15. 208-Pin LQFP Package Outline Drawing Figure 16. For pin descriptions see the EP7312 User’s Manual. © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) 27.80 (1.094) 28.20 (1.110) 1.00 (0.039) BSC 0° ...
Page 31
... Note: 1. N/C should not be grounded but left as no connects. DS508F1 High-Performance, Low-Power System on Chip EP7312 208-Pin LQFP (Top View) © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7312 D[25] 104 A[25]/DRA[2] 103 D[26] 102 A[26]/DRA[1] 101 D[27] 100 ...
Page 32
... EP7312 High-Performance, Low-Power System on Chip 208-Pin LQFP Numeric Pin Listing Pin Signal No. 1 nCS[5] 2 VDDIO 3 VSSIO 4 EXPCLK 5 WORD 6 WRITE/nSDRAS 7 RUN/CLKEN 8 EXPRDY 9 TXD[2] 10 RXD[2] 11 TDI 12 VSSIO 13 PB[7] 14 PB[6] 15 PB[5] 16 PB[4] 17 PB[3] 18 PB[2] 19 PB[1] 20 PB[0] 21 VDDIO 22 TDO 23 PA[7] 24 PA[6] 25 PA[5] 26 PA[4] 27 PA[3] 28 PA[2] ...
Page 33
... SSI1 ADC serial input O SSI1 ADC chip select Core ground Core Pwr Core power, 2.5 V Pad Gnd I/O ground Pad Pwr Digital I/O power, 3.3 V I/O PWM drive output I/O PWM drive output O SSI1 ADC serial clock O SSI1 ADC serial data output EP7312 33 ...
Page 34
... EP7312 High-Performance, Low-Power System on Chip Pin Signal No. 79 SMPCLK 80 FB[1] 81 VSSIO 82 FB[0] 83 COL[7] 84 COL[6] 85 COL[5] 86 COL[4] 87 COL[3] 88 COL[2] 89 VDDIO 90 TCLK 91 COL[1] 92 COL[0] 93 BUZ 94 D[31] 95 D[30] 96 D[29] 97 D[28] 98 VSSIO 99 A[27]/DRA[0] 100 D[27] 101 A[26]/DRA[1] 102 D[26] 103 A[25]/DRA[2] 104 ...
Page 35
... I/O ground I/O Data I/O I Battery changed sense input External power supply sense I input I Battery OK input I Power-on reset input Media change interrupt input / I internal ROM boot enable I User reset input Oscillator power in, 2 Main oscillator input O Main oscillator output Oscillator Ground EP7312 35 ...
Page 36
... EP7312 High-Performance, Low-Power System on Chip Pin Signal No. 161 WAKEUP 162 nPWRFL 163 A[6] 164 D[6] 165 A[5] 166 D[5] 167 VDDIO 168 VSSIO 169 A[4] 170 D[4] 171 A[3] 172 D[3] 173 A[2] 174 VSSIO 175 D[2] 176 A[1] 177 D[1] ...
Page 37
... Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions. DS508F1 Table 20. 208-Pin LQFP Numeric Pin Listing (Continued) Reset † Strength State 1 High 1 High 1 High © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip Type Description O Chip select 2 O Chip select 3 O Chip select 4 EP7312 37 ...
Page 38
... EP7312 High-Performance, Low-Power System on Chip 204-Ball TFBGA Package Characteristics TOP VIEW A1 CORNER SEATING PLANE C 38 Ø0. Ø0.25~0.35(204X Figure 17. 204-Ball TFBGA Package © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) BOTTOM VIEW A1 CORNER 0.65 12.35 13±0.05 Substrate Thickness : Ball Pitch : 0.65 ...
Page 39
... DRA[7] A[19]/ D[22] DRA[8] D[21] D[23] HALF D[24] WORD A[26]/ BUZ D[29] VDDIO VDDIO DRA[1] A[27]/ D[30] D[26] VDDIO DRA[0] A[25]/ D[31] D[28] D[27] DRA[2] EP7312 19 20 GNDIO A nURESET B nPOR C A[7] D D[9] E A[8] D[10] F A[9] D[11] G A[12] H A[13]/ J DRA[14] D[15] K A[16]/ ...
Page 40
... EP7312 High-Performance, Low-Power System on Chip 204-Ball TFBGA Ball Listing The list is ordered by ball location. Ball Location Name Strength A1 VDDIO A2 EXPCLK A3 nCS[3] A4 nCS[1] A5 nMWE/nSDWE A6 SDQM[2] A7 nSDCS[1] A8 DD[2] A9 FRM A10 CL[1] A11 VSSCORE A12 D[1] A13 A[2] A14 D[4] A15 A[5] A16 nPWRFL ...
Page 41
... System byte address 1 Low I/O Data I/O 1 Low O System byte address Oscillator ground PLL ground Oscillator power Oscillator power in, 2.5V Pad ground I/O ground I Battery ok input © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip Description EP7312 41 ...
Page 42
... EP7312 High-Performance, Low-Power System on Chip Ball Location Name Strength C20 nPOR D1 PB[7] D2 RXD[2] D3 VDDIO D18 VSSIO D19 nBATCHG D20 A[7] E1 PB[4] E2 TXD[2] E3 WRITE/nSDRAS E18 nMEDCHG/nBROM E19 nEXTPWR E20 D[9] F1 PB[3] F2 PB[6] F3 TDI F18 D[7] F19 A[8] F20 D[10] G1 PB[1] G2 PB[2] G3 PB[5] ...
Page 43
... Data I/O 1 Low O System byte address / SDRAM address I External interrupt I External interrupt input I UART 1 data carrier detect 1 Low I/O Data I/O 1 Low O System byte address / SDRAM address © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip Description EP7312 43 ...
Page 44
... EP7312 High-Performance, Low-Power System on Chip Ball Location Name Strength P20 D[20] R1 nEXTFIQ R2 PE[2]/CLKSEL R3 nTEST[0] R18 A[19]/DRA[8] R19 D[22] R20 A[21]/DRA[6] T1 PE[1]/BOOTSEL[1] T2 PE[0]/BOOTSEL[0] T3 nEINT[1] T18 D[21] T19 D[23] T20 A[22]/DRA[5] U1 VSSRTC U2 RTCOUT U3 RTCIN U18 HALFWORD U19 ...
Page 45
... GPIO port D / LED blinker output 1 Low O DAI/CODEC/SSI2 serial data output I SSI1 ADC serial input Core power Digital core power, 2.5V ‡ 2 I/O PWM drive output Input © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip Description EP7312 45 ...
Page 46
... PBGA Package Characteristics Note: 1) For pin locations see Table 2) Dimensions are in millimeters (inches), and controlling dimension is millimeter 3) Before beginning any new EP7312 design, contact Cirrus Logic for the latest package information. 46 Table 21. 204-Ball TFBGA Ball Listing (Continued) Reset † Type ...
Page 47
... Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip 0.85 (0.034) ±0.05 (.002) 0.40 (0.016) ±0.05 (.002) 30° TYP 2 Layer 0.36 (0.014) ±0.09 (0.004) SIDE VIEW Pin 1 Corner 17.00 (0.669) JEDEC #: MO-151 Ball Diameter: 0.50 mm ± 0. ¥ 17 ¥ 1.61 mm body EP7312 47 ...
Page 48
... EP7312 High-Performance, Low-Power System on Chip 256-Ball PBGA Pinout (Top View VDDIO nCS[4] nCS[1] SDCLK SDQM[3] nMOE/ B nCS[5] VDDIO nCS[3] VDDIO nSDCAS C VDDIO EXPCLK VSSIO VDDIO VSSIO WRITE/ D EXPRDY VSSIO VDDIO nCS[2] nSDRAS E RXD[2] PB[7] TDI WORD VSSIO RUN/ F PB[5] PB[3] VSSIO ...
Page 49
... Digital I/O power, 3.3 V Pad ground I/O ground Pad ground I/O ground Pad ground I/O ground Pad power Digital I/O power, 3.3 V Pad ground I/O ground © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip Description EP7312 49 ...
Page 50
... EP7312 High-Performance, Low-Power System on Chip Ball Location Name Strength C14 VSSIO C15 nPOR Schmitt C16 nEXTPWR D1 WRITE/nSDRAS D2 EXPRDY D3 VSSIO D4 VDDIO D5 nCS[2] D6 nMWE/nSDWE D7 nSDCS[0] D8 CL[2] D9 VSSRTC D10 D[4] D11 nPWRFL D12 MOSCIN D13 VDDIO D14 VSSIO D15 D[7] D16 D[8] E1 RXD[2] E2 PB[7] ...
Page 51
... GPIO port A Input ‡ 1 I/O GPIO port A Input Pad ground I/O ground ‡ 1 I/O GPIO port A Input ‡ 1 I/O GPIO port A Input 1 High O UART 1 transmit data out © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip Description EP7312 51 ...
Page 52
... EP7312 High-Performance, Low-Power System on Chip Ball Location Name Strength J7 CTS J8 VSSRTC J9 VSSRTC J10 A[17]/DRA[10] J11 A[16]/DRA[11] J12 A[15]/DRA[12] J13 A[14]/DRA[13] J14 nTRST J15 D[16] J16 D[17] K1 LEDDRV K2 PHDIN K3 VSSIO K4 DCD K5 nTEST[1] With p/u* K6 EINT[3] K7 VSSRTC K8 ADCIN K9 COL[4] ...
Page 53
... Pad power Digital I/O power, 3.3V I/O Real time clock oscillator input Pad power Digital I/O power, 3.3V 1 Low I/O GPIO port D 1 Low I/O GPIO port D © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip Description EP7312 53 ...
Page 54
... EP7312 High-Performance, Low-Power System on Chip Ball Location Name Strength R5 SSITXDA R6 nADCCS R7 VDDIO R8 ADCOUT R9 COL[7] R10 COL[3] R11 COL[1] R12 D[30] R13 A[27]/DRA[0] R14 A[25]/DRA[2] R15 VDDIO R16 A[24]/DRA[3] T1 VDDRTC T2 PD[7]/SDQM[1] T3 PD[6]/SDQM[0] T4 PD[3] T5 SSICLK T6 SSIRXFR T7 VDDCORE T8 DRIVE[0] ...
Page 55
... W4 T3 PD[6/SDQM[0 PD[5] © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) High-Performance, Low-Power System on Chip Type Position I/O 17 I/O 20 I/O 23 I/O 26 I/O 29 I/O 32 I/O 35 I/O 38 I/O 41 I/O 44 I/O 47 I/O 50 I/O 53 I/O 56 I I/O 80 I/O 83 I/O 86 I/O 89 I/O 92 I/O 95 EP7312 55 ...
Page 56
... EP7312 High-Performance, Low-Power System on Chip Table 23. JTAG Boundary Scan Signal Ordering (Continued) LQFP TFBGA Pin No 100 101 102 103 104 105 106 109 110 56 PBGA Signal Ball Ball V5 R3 PD[ PD[ PD[ PD[ PD[0]/LEDFLSH W8 T6 SSIRXFR Y8 K8 ADCIN V9 R6 nADCCS W10 M8 DRIVE1 ...
Page 57
... I/O 221 O 224 I/O 226 O 229 I/O 231 O 234 I/O 236 O 239 I/O 241 O 244 I/O 246 O 249 I/O 251 O 254 I/O 256 O 259 I/O 261 O 264 I/O 266 O 269 I/O 271 O 274 I/O 276 I 279 I 280 I 281 I 282 I 283 EP7312 57 ...
Page 58
... EP7312 High-Performance, Low-Power System on Chip Table 23. JTAG Boundary Scan Signal Ordering (Continued) LQFP TFBGA Pin No. 156 161 162 163 164 165 166 169 170 171 172 173 175 176 177 178 179 184 185 186 187 188 189 191 192 193 ...
Page 59
... See EP7312 Users’ Manual for pin naming / functionality. 2) For each pad, the JTAG connection ordering is input, output, then enable as applicable. DS508F1 High-Performance, Low-Power System on Chip © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7312 59 ...
Page 60
... EP7312 High-Performance, Low-Power System on Chip CONVENTIONS This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet. Acronyms and Abbreviations Table 24 lists abbreviations and acronyms used in this data sheet. Table 24. Acronyms and Abbreviations Acronym/ Definition Abbreviation A/D analog-to-digital ADC ...
Page 61
... Registers are referred to by acronym, with bits listed in brackets separated by a colon (:) (for example, CODR[7:0]), and are described in the EP7312 User’s Manual. The use of “TBD” indicates values that are “to be determined,” “n/a” designates “not available,” and “n/c” indicates a pin that is a “ ...
Page 62
... Environmental, Manufacturing, & Handling Information Model Number EP7312-CB EP7312-CB-90 (90 MHz) EP7312-IB EP7312-IB-90 (90 MHz) EP7312-CR EP7312-CR-90 (90 MHz) EP7312-IR EP7312-IR-90 (90 MHz) EP7312-CV EP7312-CV-90 (90 MHz) EP7312-IV EP7312-IV-90 (90 MHz) EP7312-CVZ (Lead Free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 62 Temperature 0 to +70 °C -40 to +85 ° +70 °C -40 to +85 °C. ...
Page 63
... SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. LINUX is a registered trademark of Linus Torvalds. Microsoft Windows and Microsoft are registered trademarks of Microsoft Corporation. DS508F1 High-Performance, Low-Power System on Chip Changes © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) EP7312 63 ...
Page 64
... EP7312 High-Performance, Low-Power System on Chip 64 © Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) DS508F1 ...