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CY8C26443-24SI
CY8C26443-24SI | |
|---|---|
| Manufacturer Part Number | CY8C26443-24SI |
| Description | IC MCU 16K FLASH 256B 28-SOIC |
| Manufacturer | Cypress Semiconductor Corp |
| Series | PSOC™ CY8C26xxx |
| CY8C26443-24SI datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
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Specifications of CY8C26443-24SI | |||
|---|---|---|---|
| Core Processor | M8C | Core Size | 8-Bit |
| Speed | 24MHz | Connectivity | SPI, UART/USART |
| Peripherals | LVD, POR, PWM, WDT | Number Of I /o | 24 |
| Program Memory Size | 16KB (16K x 8) | Program Memory Type | FLASH |
| Ram Size | 256 x 8 | Voltage - Supply (vcc/vdd) | 3 V ~ 5.25 V |
| Data Converters | A/D 1x8b, 1x11b, 1x12b; D/A 1x9b | Oscillator Type | Internal |
| Operating Temperature | -40°C ~ 85°C | Package / Case | 28-SOIC (7.5mm Width) |
| Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant | Eeprom Size | - |
| Other names | 428-1430 428-1430-5 428-1430 | ||
PrevNext
11.6
Switch Mode Pump
This feature is available on the CY8C26xxx versions
within this family. During the time Vcc is ramping from 0
Volts to POR V
(2.2V +/- 12%), IC operation is held off
trip
by the POR circuit and the Switch Mode Pump is
enabled. The pump is realized by connecting an external
inductor between the battery voltage and SMP, with an
external diode pointing from SMP to the V
must have a bypass capacitance of at least 0.1uF con-
nected to V
). This circuitry will pump Vcc to the Switch
cc
Mode Pump value specified in the Voltage Monitor Con-
trol Register (VLT_CR), shown above. Battery voltage
values down to 0.9 V during operation are supported, but
this circuitry is not guaranteed to start for battery volt-
ages below 1.2 V. Once the IC is enabled after its power
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
up and boot sequence, firmware can disable the SMP
function by writing Voltage Monitor Control Register
(VLT_CR) bit 7 to a 1.
When the IC is put into sleep mode, the power supply
pump will remain running to maintain voltage. This may
result in higher than specification sleep current depend-
pin (which
cc
ing upon application. If the user desires, the pump may
be disabled during precision measurements (such as A/
D conversions) and then re-enabled (writing B7 to 1 and
then back to 0 again). The user, however, is responsible
for making the operation happen quickly enough to guar-
antee supply holdup (by the bypass capacitor) sufficient
for continued operation.
V
Power For All Circuitry
CC
SMP
SMP
Control
Logic
SMP Reset
X
RST
Reset
Figure 32: Switch Mode Pump
Special Features of the CPU
To Rest Of
Circuitry
117
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