CY8C26443-24SI

Manufacturer Part NumberCY8C26443-24SI
DescriptionIC MCU 16K FLASH 256B 28-SOIC
ManufacturerCypress Semiconductor Corp
SeriesPSOC™ CY8C26xxx
CY8C26443-24SI datasheets

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Specifications of CY8C26443-24SI

Core ProcessorM8CCore Size8-Bit
Speed24MHzConnectivitySPI, UART/USART
PeripheralsLVD, POR, PWM, WDTNumber Of I /o24
Program Memory Size16KB (16K x 8)Program Memory TypeFLASH
Ram Size256 x 8Voltage - Supply (vcc/vdd)3 V ~ 5.25 V
Data ConvertersA/D 1x8b, 1x11b, 1x12b; D/A 1x9bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case28-SOIC (7.5mm Width)
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantEeprom Size-
Other names428-1430
428-1430-5
428-1430
  
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9.3.4
Digital Communications Type A Block xx Control Register 0 When Used as UART Trans-
mitter
Table 56:
Digital Communications Type A Block xx Control Register 0...
Bit #
7
6
POR
0
0
Read/
--
--
Write
Bit Name
Reserved
Reserved
Bit 7 : Reserved
Bit 6 : Reserved
Bit 5 : TX Complete
0 = Indicates that if a transmission has been initiated, it is still in progress
1 = Indicates that the current transmission is complete (including framing bits)
Optional interrupt source for TX UART. Reset when this register is read.
Bit 4 : TX Reg Empty
0 = Indicates TX Data register is not available to accept another byte (writing to register will cause data to be lost)
1 = Indicates TX Data register is available to accept another byte
Note that the interrupt does not occur until at least 1 byte has been previously written to the TX Data Register
Default interrupt source for TX UART. Reset when the TX Data Register (Data Register 1) is written.
Bit 3 : Reserved
Bit 2 : Parity Type
0 = Even
1 = Odd
Bit 1 : Parity Enable
0 = Parity Disabled
1 = Parity Enabled
Bit 0 : Enable
0 = Function Disabled
1 = Function Enabled
Digital Communications Type A 04 Control Register 0
Digital Communications Type A 05 Control Register 0
Digital Communications Type A Block 06 Control Register 0
Digital Communications Type A Block 07 Control Register 0
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
5
4
3
0
0
0
R
R
--
TX Reg
TX Complete
Reserved
Empty
(DCA04CR0, Address = Bank 0, 33h)
(DCA05CR0, Address = Bank 0, 37h)
(DCA06CR0, Address = Bank 0, 3Bh)
(DCA07CR0, Address = Bank 0, 3Fh)
Digital PSoC Blocks
2
1
0
0
0
0
RW
RW
RW
Parity
Parity Type
Enable
Enable
57