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CY8C26443-24SI
CY8C26443-24SI | |
|---|---|
| Manufacturer Part Number | CY8C26443-24SI |
| Description | IC MCU 16K FLASH 256B 28-SOIC |
| Manufacturer | Cypress Semiconductor Corp |
| Series | PSOC™ CY8C26xxx |
| CY8C26443-24SI datasheets |
|
Availability: In stock
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Warranty: 60 days
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Specifications of CY8C26443-24SI | |||
|---|---|---|---|
| Core Processor | M8C | Core Size | 8-Bit |
| Speed | 24MHz | Connectivity | SPI, UART/USART |
| Peripherals | LVD, POR, PWM, WDT | Number Of I /o | 24 |
| Program Memory Size | 16KB (16K x 8) | Program Memory Type | FLASH |
| Ram Size | 256 x 8 | Voltage - Supply (vcc/vdd) | 3 V ~ 5.25 V |
| Data Converters | A/D 1x8b, 1x11b, 1x12b; D/A 1x9b | Oscillator Type | Internal |
| Operating Temperature | -40°C ~ 85°C | Package / Case | 28-SOIC (7.5mm Width) |
| Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant | Eeprom Size | - |
| Other names | 428-1430 428-1430-5 428-1430 | ||
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PrevNext
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
directly into Data Register 0 (The block must be disabled
when writing this value). Data Register 1 specifies the
polynomial and width of the numbers in the sequence
(see “Specifying the Polynomial”, below). Once the input
bit stream is complete, the result may be read by first
reading Data Register 0, which returns 0, then reading
Data Register 2, which returns the actual result.
9.5.5.3
Inputs
The clock input determines the rate at which the input
sequence is processed. The data input selects the data
stream to process. It is assumed that the data is valid on
the positive edge of the clock input. The multiplexer for
selecting these inputs is controlled by the PSoC block
Input Register (DBA00IN-DCA07IN).
9.5.5.4
Outputs
Like the PRS, the CRC function drives the output serial
data stream with the most significant bit of CRC process-
ing synchronous with the input clock. Normally the CRC
output is not used. The output may be driven on the Glo-
bal Output bus or to the subsequent digital PSoC block.
The
PSoC
block
Output
Register
DCA07OU) controls output options.
9.5.5.5
Interrupts
The CRC function provides an interrupt based on the
Compare signal between Data Register 0 and Data Reg-
ister 2.
9.5.5.6
Specifying the Polynomial
Computation of an N-bit result is generally specified by a
polynomial with N+1 terms, the last of which is the X
0
term, where X
=1. For example, the widely used CRC-
16
12
CCIT 16-bit polynomial is X
+X
+X
block CRC function assumes the presence of the X
term so that the polynomial for an N-bit result can be
expressed by an N-bit rather than N+1 bit specification.
To obtain the PSoC block register specification, write an
N+1 bit binary number corresponding to the full polyno-
mial, with 1’s for each term present. The CRC-CCIT
polynomial would be 10001000000100001b. Simply
0
drop the right-most bit (the X
term) to obtain the register
specification for the PSoC block. To implement the CRC-
66
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
CCIT example, two PSoC blocks must be chained
together. Data Register 1 in the high-order PSoC block
would take the value 10001000b (88h) and the corre-
sponding register in the low-order PSoC block would
take 00010000b (10h).
9.5.5.7
Usage Notes
1.
Disabled State
When the Control Register Enable bit is set to ‘0’,
the internal block clock is turned off. A write to Data
Register 2 (Seed) is loaded directly into Data Regis-
ter 0 (LFSR) to initialize or reset the seed value. All
outputs are low and the block interrupt is held low.
2.
Reading the CRC value
After the data stream has been processed by the
LFSR, the residue is the CRC value. The current
LFSR value can only be read when the block is dis-
abled by setting the Control Register bit 0 to low.
Each byte of the current LFSR value (in the case of
a multi-byte block) must be read individually. The
Data Register 0 byte (LFSR) must be read, which
returns 0, then the Data Register 2 byte, which
returns the actual value.
(DBA00OU-
9.5.6
Universal Asynchronous Receiver
9.5.6.1
Summary
The Universal Asynchronous Receiver implements the
input half of a basic 8-bit UART. Start and Stop bits are
recognized and stripped. Parity type and parity validation
are configurable features. This function requires a Digital
Communications Type PSoC block and cannot be
chained for longer data words.
9.5.6.2
Registers
0
The function shifts incoming data into Data Register 0.
Once complete, the byte is transferred to Data Register 2
5
+1. The PSoC
from which it may be read. Data Register 2 acts as a 1
0
byte receive buffer. Data Register 1 is not used by this
function. Control Register 0 (DCA04CR0-DCA07CR0)
enables the function, provides the means to configure
parity checking, and a full set of status indications. See
the register definition for full details.
September 5, 2002
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