CY8C26443-24SI

Manufacturer Part NumberCY8C26443-24SI
DescriptionIC MCU 16K FLASH 256B 28-SOIC
ManufacturerCypress Semiconductor Corp
SeriesPSOC™ CY8C26xxx
CY8C26443-24SI datasheets

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Specifications of CY8C26443-24SI

Core ProcessorM8CCore Size8-Bit
Speed24MHzConnectivitySPI, UART/USART
PeripheralsLVD, POR, PWM, WDTNumber Of I /o24
Program Memory Size16KB (16K x 8)Program Memory TypeFLASH
Ram Size256 x 8Voltage - Supply (vcc/vdd)3 V ~ 5.25 V
Data ConvertersA/D 1x8b, 1x11b, 1x12b; D/A 1x9bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case28-SOIC (7.5mm Width)
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantEeprom Size-
Other names428-1430
428-1430-5
428-1430		  
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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
except for TX Reg Empty. TX Reg Empty is auto-
matically cleared when a byte is written to the TX
Data Register (Data Register 1).
3.
Using CPU Interrupts
TX Reg Empty status or optionally TX Complete sta-
tus generates the block interrupt. Executing the
interrupt routine does not automatically clear status.
If TX Complete is selected as the interrupt source,
Control Register 0 (status) must be read in the inter-
rupt routine to clear the status. If TX Reg Empty is
selected, a byte must be written to the TX Data Reg-
ister (Data Register 1) to clear the status. If the sta-
tus is not cleared, further interrupts will be
suppressed.
Clock Phase 0 (Mode 0, 1)
Data registered on the leading edge of the clock
Data output on the trailing edge of the clock
SS_
(required f or slav e)
Polarity=0, Mode 0
SCLK
Polarity=1, Mode 1
MOSI/MISO
Bit7
Clock Phase 1 (Mode 2, 3)
Data output on the leading edge of the clock
Data registered on the trailing edge of the clock
SS_
(optional f or slav e)
Polarity=0, Mode 2
SCLK
Polarity=1, Mode 3
MOSI/MISO
Bit7
9.5.8.2
Registers
Data Register 0 provides a shift register for both incom-
ing and outgoing data. Output data is written to Data
Register 1 (TX Data Register). When this block is idle, a
write to the TX Data Register will initiate a transmission.
Input data is read from Data Register 2 (RX Data Regis-
ter). When Data Register 0 is empty, its value is updated
from Data Register 1, if new data is available. As data
bits are shifted in, the transmit bits are shifted out. After
the 8 bits are transmitted and received by Data Register
68
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
9.5.8
SPI Master - Serial Peripheral Interface
(SPIM)
9.5.8.1
Summary
The SPI Master function provides a full-duplex synchro-
nous data transceiver that also generates a bit clock for
the data. This function requires a Digital Communica-
tions Type PSoC block. It cannot be chained for longer
data words. This Digital Communications Type PSoC
block supports SPI modes for 0, 1, 2, and 3. See
Title 15
for waveforms of the Clock Phase modes.
Bit6
Bit5
Bit4
Bit3
Bit2
Bit6
Bit5
Bit4
Bit3
Figure 15: SPI Waveforms
0, the received byte is transferred into Data Register 2
from where it can be read. Simultaneously, the next byte
to transmit, if available, is transferred from Data Register
1 into Data Register 0. Control Register 0 (DCA04CR0-
DCA07CR0) provides status information and configures
the function for one of the four standard modes, which
configure the interface based on clock polarity and
phase with respect to data.
Figure-
Bit1
Bit0
Bit7
Bit2
Bit1
Bit0
September 5, 2002

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