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CY8C26443-24SI
CY8C26443-24SI | |
|---|---|
| Manufacturer Part Number | CY8C26443-24SI |
| Description | IC MCU 16K FLASH 256B 28-SOIC |
| Manufacturer | Cypress Semiconductor Corp |
| Series | PSOC™ CY8C26xxx |
| CY8C26443-24SI datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
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Specifications of CY8C26443-24SI | |||
|---|---|---|---|
| Core Processor | M8C | Core Size | 8-Bit |
| Speed | 24MHz | Connectivity | SPI, UART/USART |
| Peripherals | LVD, POR, PWM, WDT | Number Of I /o | 24 |
| Program Memory Size | 16KB (16K x 8) | Program Memory Type | FLASH |
| Ram Size | 256 x 8 | Voltage - Supply (vcc/vdd) | 3 V ~ 5.25 V |
| Data Converters | A/D 1x8b, 1x11b, 1x12b; D/A 1x9b | Oscillator Type | Internal |
| Operating Temperature | -40°C ~ 85°C | Package / Case | 28-SOIC (7.5mm Width) |
| Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant | Eeprom Size | - |
| Other names | 428-1430 428-1430-5 428-1430 | ||
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PrevNext
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
10.6
Analog PSoC Block Clocking Options
All analog PSoC blocks in a particular Analog Column
share the same clock signal. Choosing the clocking for
an analog PSoC block is a two-step process.
1.
First, if the user wants to use the ACLK0 and
ACLK1 system-clocking signals, the digital PSoC
blocks that serve as the source for these signals
must be selected. This selection is made in the Ana-
log Clock Select Register (CLK_CR1).
10.6.1 Analog Column Clock Select Register
Table 63:
Analog Column Clock Select Register
Bit #
7
6
POR
0
0
Read/
RW
RW
Write
Acolumn3
Acolumn3
Bit Name
[1]
[0]
Bit [7:6] : Acolumn3 [1:0]
0 0 = 24V1
0 1 = 24V2
1 0 = ACLK0
1 1 = ACLK1
Bit [5:4] : Acolumn2 [1:0]
0 0 = 24V1
0 1 = 24V2
1 0 = ACLK0
1 1 = ACLK1
Bit [3:2] : Acolumn1 [1:0]
0 0 = 24V1
0 1 = 24V2
1 0 = ACLK0
1 1 = ACLK1
Bit [1:0] : Acolumn0 [1:0]
0 0 = 24V1
0 1 = 24V2
1 0 = ACLK0
1 1 = ACLK1
Analog Column Clock Select Register (CLK_CR0, Address = Bank 1, 60h)
74
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
2.
Next, the user must select the source for the
Acolumn0 , Acolumn1 , Acolumn2 , and Acolumn3
system-clocking signals. The user will choose the
clock for Acolumnx[1:0] bits in the Analog Column
Clock Select Register (CLK_CR0). Each analog
PSoC block in a particular Analog Column is
clocked from the Acolumn[x] system-clocking sig-
nal for that column. (Note that the Acolumn[x] sig-
nals have a 1:4 divider on them.)
5
4
3
0
0
0
RW
RW
RW
Acolumn2
Acolumn2
Acolumn1
[1]
[0]
[1]
2
1
0
0
0
0
RW
RW
RW
Acolumn1
Acolumn0
Acolumn0
[0]
[1]
[0]
September 5, 2002
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CY8C26233-24PI |
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|
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CY8C26233-24PVI |
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CY8C26233-24SI |
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