IC ENCORE MCU FLASH 4K 28DIP

 

Z8F0413PJ005EC

Manufacturer Part NumberZ8F0413PJ005EC
DescriptionIC ENCORE MCU FLASH 4K 28DIP
ManufacturerZilog
SeriesEncore!® XP®
Z8F0413PJ005EC datasheets

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Warranty: 60 days

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Specifications of Z8F0413PJ005EC

Core ProcessorZ8Core Size8-Bit
Speed5MHzConnectivityIrDA, UART/USART
PeripheralsBrown-out Detect/Reset, LED, POR, PWM, WDTNumber Of I /o24
Program Memory Size4KB (4K x 8)Program Memory TypeFLASH
Ram Size1K x 8Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 V
Oscillator TypeInternalOperating Temperature-40°C ~ 105°C
Package / Case28-DIP (0.600", 15.24mm)Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Eeprom Size-Data Converters-
Other names269-3484  
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Reserved—R/W bits must be 0 during writes; 0 when read.
NEWFRM—Status bit denoting the start of a new frame. Reading the UART Receive
Data register resets this bit to 0.
0 = The current byte is not the first data byte of a new frame
1 = The current byte is the first data byte of a new frame
MPRX—Multiprocessor Receive
Returns the value of the most recent multiprocessor bit received. Reading from the UART
Receive Data register resets this bit to 0.
UART Control 0 and Control 1 Registers
The UART Control 0 and Control 1 registers
properties of the UART’s transmit and receive operations. The UART Control registers
must not be written while the UART is enabled.
Table 66. UART Control 0 Register (U0CTL0)
BITS
7
6
TEN
REN
FIELD
0
0
RESET
R/W
R/W
R/W
ADDR
TEN—Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is
enabled.
0 = Transmitter disabled
1 = Transmitter enabled
REN—Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled
1 = Receiver enabled
CTSE—CTS Enable
0 = The CTS signal has no effect on the transmitter
1 = The UART recognizes the CTS signal as an enable control from the transmitter
PEN—Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSEL bit.
0 = Parity is disabled
1 = The transmitter sends data with an additional parity bit and the receiver receives an
additional parity bit
PS024314-0308
(Table 66
5
4
3
CTSE
PEN
PSEL
0
0
0
R/W
R/W
R/W
F42H
Universal Asynchronous Receiver/Transmitter
®
Z8 Encore! XP
F0823 Series
Product Specification
and
Table
67) configure the
2
1
0
SBRK
STOP
LBEN
0
0
0
R/W
R/W
R/W
107