IC ENCORE MCU FLASH 4K 28DIP

 

Z8F0413PJ005EC

Manufacturer Part NumberZ8F0413PJ005EC
DescriptionIC ENCORE MCU FLASH 4K 28DIP
ManufacturerZilog
SeriesEncore!® XP®
Z8F0413PJ005EC datasheets

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Warranty: 60 days

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Specifications of Z8F0413PJ005EC

Core ProcessorZ8Core Size8-Bit
Speed5MHzConnectivityIrDA, UART/USART
PeripheralsBrown-out Detect/Reset, LED, POR, PWM, WDTNumber Of I /o24
Program Memory Size4KB (4K x 8)Program Memory TypeFLASH
Ram Size1K x 8Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 V
Oscillator TypeInternalOperating Temperature-40°C ~ 105°C
Package / Case28-DIP (0.600", 15.24mm)Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Eeprom Size-Data Converters-
Other names269-3484  
Z8F0223SB005SG PDF datasheetZ8F0423SB005SG PDF datasheet #2
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If an initial starting value other than
registers, use the ONE-SHOT mode equation to determine the first PWM time-out period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is
represented by the following equation:
PWM Output High Time Ratio (%)
If TPOL is set to 1, the ratio of the PWM output High time to the total period is
represented by the following equation:
PWM Output High Time Ratio (%)
PWM Dual Output Mode
In PWM DUAL OUTPUT mode, the timer outputs a PWM output signal pair (basic PWM
signal and its complement) through two GPIO port pins. The timer input is the system
clock. The timer first counts up to the 16-bit PWM match value stored in the Timer PWM
High and Low Byte registers. When the timer count value matches the PWM value, the
Timer Output toggles. The timer continues counting until it reaches the Reload value
stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload value,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to
0001H
If the TPOL bit in the Timer Control register is set to 1, the Timer Output signal begins as
a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The
Timer Output signal returns to a High (1) after the timer reaches the Reload value and is
reset to
.
0001H
If the TPOL bit in the Timer Control register is set to 0, the Timer Output signal begins as
a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The
Timer Output signal returns to a Low (0) after the timer reaches the Reload value and is
reset to
.
0001H
The timer also generates a second PWM output signal Timer Output Complement. The
Timer Output Complement is the complement of the Timer Output PWM signal. A
programmable deadband delay can be configured to time delay (0 to 128 system clock
cycles) PWM output transitions on these two pins from a low to a high (inactive to active).
This ensures a time gap between the deassertion of one PWM output to the assertion of its
complement.
Follow the steps below for configuring a timer for PWM Dual Output mode and initiating
the PWM operation:
1. Write to the Timer Control register to:
Disable the timer
–
Configure the timer for PWM Dual Output mode. Setting the mode also involves
–
writing to TMODEHI bit in TxCTL1 register
Set the prescale value
–
PS024314-0308
is loaded into the Timer High and Low Byte
0001H
Reload Value
------------------------------------------------------------------ -
=
PWM Value
=
----------------------------------- - 100
Reload Value
and counting resumes.
®
Z8 Encore! XP
F0823 Series
Product Specification
–
PWM Value
×
100
Reload Value
×
Timers
73

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