LH7A404N0F000B2 Sharp Microelectronics, LH7A404N0F000B2 Datasheet
LH7A404N0F000B2
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LH7A404N0F000B2
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LH7A404N0F000B2 Summary of contents
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Data Sheet FEATURES • ARM922T™ Core: – 32-bit ARM9TDMI™ RISC Core (200 MHz) – 16KB Cache: 8KB Instruction Cache and 8KB Data Cache – MMU (Windows CE™ Enabled) • 80KB On-Chip Memory • Vectored Interrupt Controller • External Bus Interface ...
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LH7A404 ARM 922T ASYNCHRONOUS MEMORY CONTROLLER EXTERNAL PCMCIA/CF CONTROLLER BUS INTERFACE SYNCHRONOUS MEMORY CONTROLLER LCD AHB BUS COLOR LCD CONTROLLER ADVANCED LCD INTERFACE (ALI) USB HOST INTERFACE HIGH-PERFORMANCE 2 14.7456 MHz 32.768 kHz OSCILLATOR, PLL1 and PLL2, POWER MANAGEMENT, and ...
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System-on-Chip CABGA SIGNAL E10 E11 H10 H11 K5 K8 K13 K16 L5 VDD I/O Ring Power L8 L13 L16 N10 N11 T10 T11 U18 J9 J10 J11 J12 K9 K10 K11 K12 L9 VSS I/O Ring Ground L10 L11 ...
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LH7A404 Table 1. LH7A404 Functional Pin List (Cont’d) CABGA SIGNAL E6 E15 F5 F16 J16 VSSC Core Ground M5 R5 R16 T6 T15 Y17 VDDA Analog Power for PLL1 and PLL2 W17 V16 VSSA Analog Ground for PLL1 and PLL2 ...
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System-on-Chip Table 1. LH7A404 Functional Pin List (Cont’d) CABGA SIGNAL N19 D0 P20 D1 N18 D2 N20 D3 M16 D4 M18 D5 L18 D6 L17 D7 L19 D8 J19 D9 K17 D10 J18 D11 H19 D12 G20 D13 G19 ...
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LH7A404 Table 1. LH7A404 Functional Pin List (Cont’d) CABGA SIGNAL N17 A2/SA0 M19 A3/SA1 M20 A4/SA2 L20 A5/SA3 M17 A6/SA4 K18 A7/SA5 K20 A8/SA6 Asynchronous Address Bus and Synchronous Address Bus K19 A9/SA7 J20 A10/SA8 H20 A11/SA9 J17 A12/SA10 H18 ...
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System-on-Chip Table 1. LH7A404 Functional Pin List (Cont’d) CABGA SIGNAL C14 SCKE3 Clock Enable 3 for Synchronous Memory D14 SCLK Synchronous Memory Clock A13 nBLE0 Byte Lane Enable 0 U9 nBLE1 Byte Lane Enable 1 Y7 nBLE2 Byte Lane ...
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LH7A404 Table 1. LH7A404 Functional Pin List (Cont’d) CABGA SIGNAL V1 PC7 GPIO Port C7 Y11 PD0/LCDVD8 U10 PD1/LCDVD9 W12 PD2/LCDVD10 V11 PD3/LCDVD11 • GPIO Port D[7:0] • LCD Video Data Interface W11 PD4/LCDVD12 U11 PD5/LCDVD13 V12 PD6/LCDVD14 Y12 PD7/LCDVD15 ...
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System-on-Chip Table 1. LH7A404 Functional Pin List (Cont’d) CABGA SIGNAL • GPIO Port G2 PG2/ Y3 • I/O Read Strobe for PC Card (PCMCIA or nPCIOR CompactFlash) in Single or Dual Card mode • GPIO Port G3 PG3/ U5 ...
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LH7A404 Table 1. LH7A404 Functional Pin List (Cont’d) CABGA SIGNAL • GPIO Port H7 PH7/ U7 • Status Read Enable for PC Card (PCMCIA or nPCSTATRE CompactFlash) in Single or Dual Card mode LCDFP/ • LCD Frame Pulse T4 LCDSPS ...
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System-on-Chip Table 1. LH7A404 Functional Pin List (Cont’d) CABGA SIGNAL • Audio Codec (AC97) Input B6 ACIN • Audio Codec (ACI) Input A5 MMCCLK MultiMediaCard Clock (20 MHz MAX.) D7 MMCCMD MultiMediaCard Command C6 MMCDATA0 MultiMediaCard Data 0 B5 ...
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LH7A404 Table 1. LH7A404 Functional Pin List (Cont’d) CABGA SIGNAL V15 AN6 ADC channel 6 W15 AN7 ADC channel 7 T13 AN8 ADC channel 8 Y14 AN9 ADC channel 9 E12 SCIO Smart Card Interface I/O A11 SCCLK Smart Card ...
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System-on-Chip CABGA RESET LCD PIN STATE SIGNAL SINGLE PANEL L4 PA1 LCDVD17 M2 PA0 LCDVD16 Y12 PD7 LCDVD15 V12 PD6 LCDVD14 U11 PD5 LCDVD13 W11 PD4 LCDVD12 V11 PD3 LCDVD11 W12 PD2 LCDVD10 U10 PD1 LCDVD9 Y11 PD0 LCDVD8 ...
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LH7A404 Table 4. CABGA Numerical Pin List CABGA SIGNAL A1 PE7/SCDATEN 95 mV/ns A2 DACK1 95 mV/ns A3 DREQ0 A4 MMCDATA2 110 mV/ns A5 MMCCLK 110 mV/ns A6 ACSYNC 110 mV/ns A7 PF6/INT6/PCRDY1 110 mV/ns A8 PF2/INT2 110 mV/ns A9 ...
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System-on-Chip Table 4. CABGA Numerical Pin List (Cont’d) CABGA SIGNAL E11 VDD E12 SCIO 95 mV/ns E13 DQM1 95 mV/ns E14 VDDC E15 VSSC E16 nSCS3 95 mV/ns E17 A21 95 mV/ns E18 D20 95 mV/ns E19 D18 95 ...
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LH7A404 Table 4. CABGA Numerical Pin List (Cont’d) CABGA SIGNAL M3 PA2 110 mV/ns M4 PA3 110 mV/ns M5 VSSC M9 VSS M10 VSS M11 VSS M12 VSS M16 D4 95 mV/ns M17 A6/SA4 95 mV/ns M18 D5 95 mV/ns ...
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System-on-Chip Table 4. CABGA Numerical Pin List (Cont’d) CABGA SIGNAL V6 PH0/PCRESET1 110 mV/ns V7 PH6/nAC97RESET 110 mV/ns V8 LCDVD0 95 mV/ns V9 LCDENAB/LCDM 95 mV/ns V10 PE2/LCDVD6 95 mV/ns V11 PD3/LCDVD11 95 mV/ns V12 PD6/LCDVD14 95 mV/ns V13 ...
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LH7A404 ROM FLASH SRAM SDRAM COMPACT FLASH PC PCMCIA CARD DEVICE HOST SYSTEM DESCRIPTIONS ARM922T Processor The LH7A404 microcontroller features the ARM922T cached core with an Advanced High-performance Bus (AHB) interface. The processor is a member of the ARM9T family ...
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System-on-Chip Power Modes The LH7A404 has three operational states: Run, Halt, and Standby. During Run all clocks are hardware enabled and the processor is clocked. In the Halt mode the device is functioning, but the processor clock is halted ...
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LH7A404 AMBA APB BUS The AMBA APB provides a lower-bandwidth bus for peripherals accessed less frequently. This reduces the loading on the AHB, allowing it to run faster to maxi- mize system performance, while the APB can operate at a ...
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System-on-Chip BOOT DEVICE External device 8-bit interface, 3-byte address NAND Flash 8-bit interface, 4-byte address NAND Flash 8-bit interface, 5-byte address NAND Flash 16-bit interface, 3-byte address NAND Flash 16-bit interface, 4-byte address NAND Flash 16-bit interface, 5-byte address ...
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LH7A404 External Bus Interface The ARM922T, LCD controller, and DMA engine have access to an external memory system. The LCD controller has access to an internal frame buffer in embedded SRAM and an extension buffer in Synchro- nous Memory for ...
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System-on-Chip Embedded SRAM The LH7A404 incorporates 80KB of embedded SRAM. This embedded memory is used for storing code, data, or LCD frame data and is contiguous with external SDRAM. The 80KB is large enough to store a QVGA frame ...
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LH7A404 SD/MMC INTERFACE DESCRIPTION The SD/MMC controller uses the three-wire signal bus (clock, command, and data) to input and output data to and from the MMC, and to configure and acquire status information from the card. The SD con- troller ...
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System-on-Chip The DMA Controller features: • Two dedicated channels for M2M and external M2P/P2M • Ten fully independent, programmable DMA control- ler internal M2P/P2M channels (5 Tx and 5 Rx) • Channels assignable to one of a number of ...
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LH7A404 Color LCD Controller The LH7A404’s LCD Controller is programmable to support up to 1,024 × 768, 16-bit color LCD panels. It interfaces directly to STN, color STN, TFT, AD-TFT, and HR-TFT panels. Unlike other LCD controllers, the LH7A404’s LCD ...
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System-on-Chip UART/IrDA The LH7A404 contains three UARTs; UART1, UART2, and UART3. The UART performs: • Serial-to-Parallel conversion on data received from the peripheral device • Parallel-to-Serial conversion on data transmitted to the peripheral device. The transmit and receive paths ...
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LH7A404 • Battery voltage sense in addition to normal direct voltage inputs • A 9-channel multiplexer for routing user-selected inputs to A/D • × 16 FIFO for 10-bit digital output of A/D • A pen-down sensor to generate ...
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System-on-Chip ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings PARAMETER DC Core Supply Voltage (VDDC) DC I/O Supply Voltage (VDD) DC Analog Supply Voltage (VDDA) DC Analog Supply Voltage (VDDAD) Storage Temperature NOTE: These stress ratings are only for transient conditions. Oper- ...
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LH7A404 250 245 240 235 230 225 220 215 210 205 200 25 35 Figure 5. Temperature/Voltage/Speed Chart ° TEMP ( C) Version 1.0 32-Bit System-on-Chip 1.89 V (+5%) 1.80 V 1.71 V (-5 ...
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System-on-Chip DC/AC SPECIFICATIONS Unless otherwise noted, all data provided under commercial DC/AC specifications are based on -40°C to +85°C, VDDC = 1 1.9 V, VDD = 3 3.6 V, VDDA = 1 1.9 ...
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LH7A404 Analog-To-Digital Converter Electrical Characteristics Table 8 shows the derated specifications for extended temperature operation. See Figure 6 for the ADC transfer characteristics. Table 8. ADC Electrical Characteristics at Industrial Operating Range PARAMETER A/D Resolution Throughput Conversion Acquisition Time Data ...
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System-on-Chip 1024 1023 1022 1021 1020 1019 1018 9 8 CENTER OF A STEP OF THE ACTUAL 7 TRANSFER CURVE LSB OFFSET ERROR DNL AC Test Conditions PARAMETER DC I/O ...
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LH7A404 CURRENT CONSUMPTION BY OPERATING MODE Current consumption can depend on a number of parameters. To make these data more usable, the val- ues presented in Table 9 were derived under the con- ditions described here. Maximum Specified Value The ...
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System-on-Chip AC Specifications (Commercial) All signals described in Table 11 relate to transi- tions following an internal reference clock signal. The illustration in Figure 7 represents all cases of these sets of measurement parameters. The reference clock signals in ...
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LH7A404 SIGNAL TYPE LOAD ASYNCHRONOUS MEMORY INTERFACE SIGNALS (+ wait states × C) Output 50 pF Output 50 pF A[27:0] Output Output 50 pF D[31:0] Input nCS[3:0]/CS[7:6] Output 30 pF tAS (Write) tAS (Read) nWE[3:0] Output 30 ...
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System-on-Chip Table 11. AC Signal Characteristics (Cont’d) SIGNAL TYPE LOAD nPCOE Output 30 pF nPCWE Output 30 pF PCDIR Output 30 pF MMCCMD Output 100 pF MMCDATA Output 100 pF MMCDATA Input MMCCMD Input ACOUT Output 30 pF ACIN ...
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LH7A404 SMC Waveforms Figure 8 and Figure 9 show waveforms and timing for an external asynchronous memory Write. Note that the deassertion of nWE can precede the deassertion of 'C' HCLK A[27:0] D[31:0] nCSx nWE Figure 8. External Asynchronous Memory ...
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System-on-Chip ' HCLK A[27:0] D[31:0] tAS nCSx nWE 0 WAIT STATE Figure 9. External Asynchronous Memory Write, Four Wait States (BCRx:WST1 = 0b100) Data Sheet tWC VALID ADDRESS tDW VALID DATA tAW ...
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LH7A404 'C' HCLK A[27:0] D[31:0] nCSx nOE Figure 10. External Asynchronous Memory Read, Zero Wait States (BCRx:WST1 = 0b000 tRC VALID ADDRESS DATA tAA LATCHED HERE VALID DATA tAS tCO tOE Version 1.0 32-Bit System-on-Chip ...
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System-on-Chip ' HCLK A[27:0] tAA D[31:0] tCO tAS nCSx tOE nOE Figure 11. External Asynchronous Memory Read, Four Wait States (BCRx:WST1 = 0b100) Data Sheet tRC VALID ADDRESS DATA LATCHED HERE VALID DATA ...
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LH7A404 Synchronous Memory Controller Waveforms Figure 12 shows the waveform and timing for a Syn- chronous Burst Read (page already open). Figure 13 shows the waveform and timing for synchronous mem- ory to activate a bank and Write. SCLK SDRAMcmd ...
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System-on-Chip SSP Waveforms The Synchronous Serial Port (SSP) supports three data frame formats: • Texas Instruments SSI • Motorola SPI • National Semiconductor MICROWIRE Each frame format is between 4 and 16 bits in length, depending upon the programmed ...
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LH7A404 For Motorola SPI, the serial frame pin (SSPFRM) is active LOW. The SPO and SPH bits in SSP Control Register 0 determine SSPCLK and SSPFRM operation SSPCLK nSSPFRM tISSPIN SSPRXD MSB tOVSSPFRM tOVSSPOUT tOHSSPOUT SSPTXD MSB NOTE ...
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System-on-Chip SSPCLK nSSPFRM SSPTXD/ SSSRXD Figure 19. Motorola SPI Frame Format (Continuous Transfer) with SPO = 0 and SPH = 1 SSPCLK nSSPFRM SSPTXD/ SSSRXD Figure 20. Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH ...
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LH7A404 SSPCLK nSSPFRM SSPTXD/ LSB SSPRXD Figure 22. Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH = 0 SSPCLK nSSPFRM SSPRXD Q MSB SSPTXD MSB NOTE undefined. Figure 23. Motorola SPI Frame Format (Single ...
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System-on-Chip For National Semiconductor MICROWIRE format, the serial frame pin (SSPFRM) is active LOW. Both the SSP and external slave device drive their output data on the falling edge of the clock, and latch data from the other device ...
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LH7A404 PC Card (PCMCIA) Waveforms Figure 26 shows the waveforms for PCMCIA Read transactions and Figure 27 shows the waveforms and timing for Write transactions. HCLK A[25:0] nPCREG nPCCEx (See Note 2) PCDIR D[31:0] nPCOE NOTES: 1. Precharge time, access ...
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System-on-Chip HCLK A[25:0] nPCREG nPCCEx (See Note 2) PCDIR D[15:0] nPCWE NOTES: 1. Precharge time, access time, and hold time are programmable wait-state times. 2. nPCCE1 nPCCE2 TRANSFER TYPE 0 0 Common Memory 0 1 Attribute Memory 1 0 ...
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LH7A404 MMC Interface Waveforms Figure 28 shows the waveforms and timing for an MMC command or data Write. Figure 29 shows the wave- forms and timing for an MMC command or data Read. MMCCLK MMCCMD MMCDATA MMCCLK MMCCMD MMCDATA ACBITCLK ...
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System-on-Chip Audio Codec Interface (ACI) Timing The timing for the Audio Codec Interface are shown in Figure 31 and Figure 32. Transmit data is clocked on the rising edge of ACBITCLK (whether transmitted by ACBITCLK ACSYNC/ACOUT ACBITCLK ACSYNC BIT ...
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LH7A404 Clock and State Controller (CSC) Waveforms Figure 33 shows the behavior of the LH7A404 when coming out of Reset or Power-On. Figure 34 shows external reset timing, and Table 12 gives the timing parameters. PARAMETER tOSC32 (32 kHz) Oscillator ...
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System-on-Chip Recommended Oscillator Circuit Design Figure 35 and Figure 36 show the recommended oscillator design for both the 32.768 kHz and 14.7456 MHz clocks. INTERNAL TO THE LH7A404 EXTERNAL TO THE LH7A404 NOTES parallel-resonant type ...
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LH7A404 INTERNAL TO THE LH7A404 EXTERNAL TO THE LH7A404 NOTES parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified load capacitance (CL). 3. ...
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System-on-Chip Printed Circuit Board Layout Practices LH7A404 POWER SUPPLY DECOUPLING The LH7A404 has separate power and ground pins for different internal circuitry sections. The VDD and VSS pins supply power to I/O buffers, while VDDC and VSSC supply power ...
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LH7A404 PACKAGE SPECIFICATIONS 324-BALL CABGA TOP VIEW A1 BALL PAD CORNER BOTTOM VIEW (324 solder balls 0.90 NOTE: Dimensions in mm. Figure 38. 324-Ball CABGA Package Specification 56 0.10 17. BALL PAD CORNER ...
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System-on-Chip CONTENT REVISIONS This document contains the following changes to content, causing it to differ from previous versions. PAGE PARAGRAPH OR DATE NO. ILLUSTRATION 3-20 Tables Figure 30 9/16/03 54-56 Figure 33 Figure ...
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LH7A404 PAGE PARAGRAPH OR DATE NO. ILLUSTRATION 1 Text 1, 30, 31 Text 4 Table 1 13 Table 3 14-16 Pin List Table 5 21 Table 6 4/1/04 34 Table 7 36 Table 9 37 Table 9 54 Text Various ...
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