ZLP32300H4832G Zilog, ZLP32300H4832G Datasheet
ZLP32300H4832G
Specifications of ZLP32300H4832G
ZLP32300H4832G
Related parts for ZLP32300H4832G
ZLP32300H4832G Summary of contents
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... Crimzon ZLP32300 ® Z8 OTP MCU with Infrared Timers Product Specification PS020823-0208 Copyright ©2008 by Zilog ® , Inc. All rights reserved. www.zilog.com ...
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... TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. PS020823-0208 ...
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Revision History Each instance in the Revision History table reflects a change to this document from its previous revision. For more details, refer to the corresponding pages or appropriate link in the table. Revision Date Level February 23 2008 January ...
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Table of Contents Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Architectural Overview ® Zilog’s Crimzon microcontrollers. With 237 B of general-purpose RAM and OTP, Zilog’s CMOS microcontrollers offer fast-executing, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/reception, and internal key-scan pull-up transistors. The Crimzon ZLP32300 architecture (see microcontroller core with an Expanded Register File allowing access to register-mapped peripherals, input/output (I/O) circuits, and powerful counter/timer circuitry ...
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Development Features Table 2 lists the features of Crimzon ZLP32300 family. Table 2. Crimzon ZLP32300 MCU Features Device Crimzon ZLP32300 *General purpose The additional features include: • Low power consumption–11 mW (typical) • Three standby modes: STOP—1.7 µA (typical) – ...
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Port 2: 0–7 pull-up transistors – EPROM Protection – WDT enabled at POR – Functional Block Diagram Figure 1 displays the Crimzon ZLP32300 MCU functional block diagram. P00 4 P01 P02 P03 I/O Nibble Port 0 Programmable P04 4 P05 ...
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SCLK Clock Divider Edge Input Glitch Detect Filter Circuit PS020823-0208 HI16 LO16 8 16-Bit T16 16 8 TC16H TC16L HI8 LO8 8 8-Bit T8 8 TC8H TC8L Figure 2. Counter/Timers Diagram ® Crimzon ZLP32300 Product Specification ...
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Pin Description The pin configuration for the 20-pin PDIP/SOIC/SSOP is displayed in described in Table in Figure 4 and described in pin SSOP versions are displayed in P25 P26 P27 P07 V XTAL2 XTAL1 P31 P32 P33 Figure 3. 20-Pin ...
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XTAL2 XTAL1 Figure 4. 28-Pin PDIP/SOIC/SSOP Pin Configuration Table 4. 28-Pin PDIP/SOIC/SSOP Pin Identification Pin No 1-3 4 11- 19- 24-28 PS020823-0208 1 P25 28 P24 2 P26 27 P23 ...
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XTAL2 XTAL1 Figure 5. 40-Pin PDIP Pin Configuration PS020823-0208 P25 2 P24 3 38 P26 P23 37 P27 4 P22 5 36 P04 P21 35 P05 6 P20 7 34 P06 P03 33 P14 8 ...
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XTAL2 XTAL1 Figure 6. 48-Pin SSOP Pin Configuration Table 5. 40- and 48-Pin Configuration 40-Pin PDIP PS020823-0208 P25 P26 P24 ...
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Table 5. 40- and 48-Pin Configuration (Continued) 40-Pin PDIP ...
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Table 5. 40- and 48-Pin Configuration (Continued) 40-Pin PDIP No Pin Functions XTAL1 Crystal 1 (Time-Based Input) This pin connects a parallel-resonant crystal or ceramic resonator to the on-chip oscillator input. Additionally, an optional external single-phase clock can be coded ...
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ONE floating port and reads back as ZERO. The following instruction sets P00-P07 all Low. AND P0,#%F0 Port 0 (P00–P07) Port 8-bit, bidirectional, CMOS-compatible port. These eight I/O ...
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ZLP32300 OTP Open-Drain I/O Out In Port 1 (P17–P10) Port 1 can be configured for standard port input or output mode (see or Stop Mode Recovery, Port 1 is configured as an input port. The output drivers are either push-pull ...
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ZLP32300 OTP Open-Drain OEN Out In Port 2 (P27–P20) Port 8-bit, bidirectional, CMOS-compatible I/O port (see lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. A ...
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ZLP32300 OTP Open-Drain I/O Out In Port 3 (P37–P30) Port 8-bit, CMOS-compatible fixed I/O port (see fixed input (P33–P30) and four fixed output (P37–P34), which can be configured under software control for interrupt and as output from ...
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P31 (AN1) Pref1 P32 (AN2) P33 (REF2) From Stop Mode Recovery Source of SMR Two on-board comparators process analog signals on P31 and P32, with reference to the voltage on Pref1 and P33. The Analog function is enabled by programming ...
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T8 and T16 Common Functions—CTR1(0D)01h IRQ modes are described in Note: Comparators are powered down by entering STOP mode. For P31–P33 to be used in a Stop Mode Recovery source, these inputs must be placed into DIGITAL mode. 2 ...
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P34 T8_Out P31 P31 + - P30 (Pref1) P32 P32 + - P33 Figure 11. Port 3 Counter/Timer Output Configuration PS020823-0208 CTR0, D0 PCON MUX P3M D1 Comp1 CTR2, D0 Out 35 MUX T16_Out CTR1, D6 ...
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Comparator Inputs In ANALOG mode, P31 and P32 have a comparator front end. The comparator reference is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its correspond- ing IRQ1 are diverted to the SMR ...
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Functional Description This device incorporates special functions to enhance the Z8 functionality in consumer and battery-operated applications. Program Memory This device addresses OTP memory. The first 12 bytes are reserved for interrupt vectors. These locations contain the ...
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Location of first Byte of instruction executed after RESET Interrupt Vector (Lower Byte) Interrupt Vector (Upper Byte) Figure 12. Program Memory Map (32 K OTP) Expanded Register File The register file has been expanded to allow for additional system control ...
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RP select the working register group. Bits 3–0 of register RP select the expanded register file bank. Note: An expanded register bank is also referred expanded register group (see Figure 13). PS020823-0208 ® Crimzon ZLP32300 Product ...
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Register Pointer Working Register Group Pointer Register File (Bank 0)** Expanded Reg. Bank 0/Group ( (0) ...
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The upper nibble of the register pointer (see group bytes in the register file, is accessed out of the possible 256. The lower nibble selects the expanded register file bank and, in the case of the Crimzon ZLP32300 ...
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LD LD for access to bank D register group 0) LD expanded register bank D and working group 7 of bank 0 for access CTRL2→register 71h LD ; CTRL2→register 71h Register File The register file (bank 0) consists ...
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Figure 15. Register Pointer—Detail Stack The internal register file is used for the stack. An 8-bit Stack Pointer SPL (R255) is used for the internal ...
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T8_Capture_LO—L08(D)0Ah This register holds the captured data from the output of the 8-bit Counter/Timer0. Typically, this register holds the number of counts when the input signal is 0. Field T8_Capture_L0 T16_Capture_HI—HI16(D)09h This register holds the captured data from the output ...
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Counter/Timer8 High Hold Register—TC8H(D)05h Field T8_Level_HI Counter/Timer8 Low Hold Register—TC8L(D)04h Field T8_Level_LO CTR0 Counter/Timer8 Control Register—CTR0(D)00h Table 7 lists and briefly describes the fields for this register. Table 7. CTR0(D)00h Counter/Timer8 Control Register Field Bit Position T8_Enable 7------- Single/Modulo-N -6------- ...
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T8 Enable This field enables T8 when set (written Single/Modulo-N When set to 0 (Modulo-N), the counter reloads the initial value when the terminal count is reached. When set to 1 (single-pass), the counter stops when the terminal ...
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Table 8. CTR1(0D)01h T8 and T16 Common Functions Field Bit Position Mode 7------- P36_Out/ -6------ Demodulator_Input T8/T16_Logic/ --54---- Edge _Detect Transmit_Submode/ ----32-- Glitch_Filter Initial_T8_Out/ ------1- Rising Edge PS020823-0208 Product Specification Value Description R/W 0* TRANSMIT Mode 1 DEMODULATION Mode R/W ...
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Table 8. CTR1(0D)01h T8 and T16 Common Functions (Continued) Field Bit Position Initial_T16_Out/ -------0 Falling_Edge *Default at Power-On Reset **Default at Power-On Reset. Not reset with a Stop Mode Recovery. Mode If the result is 0, the counter/timers are in ...
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Initial_T8_Out/Rising_Edge In TRANSMIT mode the output set to 0 when it starts to count the out- put set to 1 when it starts to count. When the counter is not ...
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Table 9. CTR2(D)02h: Counter/Timer16 Control Register (Continued) Field Bit Position T16 _Clock ---43--- Capture_INT_Mask -----2-- Counter_INT_Mask ------1- P35_Out -------0 *Indicates the value upon Power-On Reset. **Indicates the value upon Power-On Reset. Not reset with a Stop Mode Recovery. T16_Enable This ...
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P35_Out This bit defines whether P35 is used as a normal output pin or T16 output. CTR3 T8/T16 Control Register—CTR3(D)03h Table 10 lists and briefly describes the fields for this register. This register allows the T and T counters to ...
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P31 MUX P20 CTR1 CTR1 D6 D3 TRANSMIT Mode Before T8 is enabled, the output of T8 depends on CTR1, D1 T8_OUT T8_OUT is 0. See PS020823-0208 CTR1 ...
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Reset T8_Enable Bit Set Timeout Status Bit (CTR0 D5) and Generate Timeout_Int if Enabled Figure 17. TRANSMIT Mode Flowchart PS020823-0208 T8 (8-Bit) TRANSMIT Mode No T8_Enable Bit Set CTR0, D7 Yes 0 CTR1, D1 Value Load TC8L Set T8_OUT Reset ...
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When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, D1). If the initial value (CTR1, D1 TC8L is loaded; otherwise, TC8H is loaded into the counter. In SINGLE-PASS mode (CTR0, D6), T8 counts down ...
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Using the same instructions for stopping the counter/timers and setting the status bits is Caution: not recommended. Two successive commands are necessary. First, the counter/timers must be stopped. Sec- ond, the status bits must be reset. These commands are required ...
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D1). T8 then continues counting from (see Figure 21 and Positive Figure 21. DEMODULATION Mode Count Capture Flowchart PS020823-0208 Figure 22). T8 (8-Bit) Count Capture T8 Enable (Set by User) No Yes Edge ...
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Disable TC8 Figure 22. DEMODULATION Mode Flowchart PS020823-0208 T8 (8-Bit) DEMODULATION Mode T8 Enable CTR0 Yes → TC8 FFh First Edge Present No Yes Enable TC8 T8_Enable Bit Set No Yes No Edge Present Yes T8 Timeout Set ...
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T16 TRANSMIT Mode In NORMAL or PING-PONG mode, the output of T16 when not enabled, is dependent on CTR1, D0 T16_OUT T16_OUT is 0. You can force ...
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Do not load these registers at the time the values are to be loaded into the counter/timer Caution: to ensure known operation. An initial count not allowed. An initial count of 0 causes T16 to count from ...
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This T16 mode is generally used to measure space time, the length of time between bursts of carrier signal (marks CTR2 Is 1 T16 ignores the subsequent edges in the input signal and continues counting down. A ...
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Initiating PING-PONG Mode First, make sure both counter/timers are not running. Set T8 into SINGLE-PASS mode (CTR0, D6), set T16 into SINGLE-PASS mode (CTR2, D6), and set the PING-PONG mode (CTR1, D2; D3). These instructions can be in random order. ...
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Mask Register (globally or individually) enables or disables the six interrupt requests. The source for IRQ is determined by bit 1 of the Port 3 mode register (P3M). When in DIGITAL mode, Pin P33 is the source. When ...
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Table 11. Interrupt Types, Sources, and Vectors Name Source IRQ0 P32 IRQ1 P33 IRQ2 P31, T IRQ3 T16 IRQ4 T8 IRQ5 LVD When more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by the ...
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... MHz *Note: preliminary value. Figure 29. Oscillator Configuration Zilog’s IR MCU supports crystal, resonator, and oscillator. Most resonators have a frequency tolerance of less than ±0.5%, which is enough for remote control application. Resonator has a very fast startup time, which is around few hundred microseconds. Most crystals have a frequency tolerance of less than 50 ppm (± ...
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For both resonator and crystal oscillator, the oscillation ground must go directly to the ground pin of the microcontroller. The oscillation ground must use the shortest distance from the microcontroller ground pin and it must be isolated from other connections. ...
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Port Configuration Port Configuration Register The Port Configuration (PCON) register (see on Port located in the expanded register 2 at Bank F, location 00. PCON(FH)00h Default setting after reset Figure 30. Port Configuration ...
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Stop Mode Recovery Stop Mode Recovery Register (SMR) This register selects the clock divide value and determines the mode of Stop Mode Recov- ery (see Figure 31). All bits are write only except bit 7, which is read only. Bit ...
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SCLK/TCLK Divide-by-16 Select (D0 the SMR controls a divide-by-16 prescaler of SCLK/TCLK (see control selectively reduces device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources interrupt logic). After Stop Mode Recovery, this ...
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Table 13. SMR2(F)0Dh:Stop Mode Recovery Register 2* (Continued) Field Source Reserved *Port pins configured as outputs are ignored as an SMR recovery source. † Indicates the value upon Power-On Reset. PS020823-0208 Bit Position Value Description † W 000 A. POR ...
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SMR VCC SMR P31 SMR P32 SMR P33 SMR P27 SMR P20 P23 SMR P20 P27 SMR D6 To ...
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Table 14. Stop Mode Recovery Source SMR:432 Note: Any Port 2 bit defined ...
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Stop Mode Recovery Register 2 (SMR2) This register determines the mode of Stop Mode Recovery for SMR2 (see SMR2(0F) used in conjunction with SMR, either of the two specified events causes a Stop ...
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Watchdog Timer Mode Watchdog Timer Mode Register (WDTMR) The Watchdog Timer is a retriggerable one-shot timer that resets the Z8 terminal count. The WDT must initially be enabled by executing the WDT instruction. On subsequent executions of the WDT instruction, ...
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WDT Time Select (D0, D1) This bit selects the WDT time period configured as indicated in Table 15. Watchdog Timer Time Select WDTMR During Halt (D2) This bit ...
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Clock Filter XTAL Internal RC Oscillator. Low Operating V + Voltage Det. DD VBO - WDT From Stop Mode 12-ns Glitch Filter Recovery Source Stop Delay Select (SMR) * CLR1 and CLR2 enable the WDT/POR and 18 Clock Reset ...
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Table 16. EPROM Selectable Options Port 00–03 Pull-Ups Port 04–07 Pull-Ups Port 10–13 Pull-Ups Port 14–17 Pull-Ups Port 20–27 Pull-Ups EPROM Protection Watchdog Timer at Power-On Reset ON/OFF Voltage Brownout/Standby An on-chip Voltage Comparator checks that the V operation of ...
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Voltage Detection and Flags The Voltage Detection register (LVD, register 0Ch at the expanded register bank 0Dh) offers an option of monitoring the LVD register is set. Once Voltage Detection is enabled, the V real time. The ...
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Expanded Register File Control Registers (0D) The expanded register file control registers (0D) are displayed in Figure 41. CTR0(0D)00H *Default setting after reset. **Default setting after reset. Not reset with a Stop Mode Recovery. Figure 37. TC8 ...
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CTR1(0D)01H *Default setting after reset **Default setting after Reset. Not reset with a Stop Mode Recovery. Figure 38. T8 and T16 Common Control Functions ((0D)01H: Read/Write) PS020823-0208 ® Crimzon ZLP32300 Product Specification ...
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Ensure to differentiate the TRANSMIT mode from DEMODULATION Notes: mode. Depending on which of these two modes is operating, the CTR1 bit has different functions. 2. Changing from one mode to another cannot be performed without disabling the counter/timers. ...
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CTR3(0D)03H *Default setting after reset. **Default setting after reset. Not reset with a Stop Mode Recovery. Figure 40. T8/T16 Control Register (0D)03H: Read/Write (Except Where Noted) Note: If Sync Mode is enabled, the first pulse of T8 ...
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LVD(0D)0CH *Default setting after reset. Figure 41. Voltage Detection Register Note: Do not modify register P01M while checking a low-voltage condition. Switching noise of both Ports 0 and 1 together might trigger the LVD Flag. PS020823-0208 D4 ...
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Expanded Register File Control Registers (0F) The expanded register file control registers (0F) are displayed in Figure 55 on page 74. PCON(0F)00H *Default setting after reset Figure 42. Port Configuration Register (PCON)(0F)00H: Write Only) PS020823-0208 D4 D3 ...
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SMR(0F)0BH *Default setting after Reset * *Set after Stop Mode Recovery * * *At the XOR gate input * * * *Default setting after Reset. Must using a crystal or resonator clock source. * ...
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SMR2(0F)0DH used in conjunction with SMR, either of the two specified events causes a Stop Mode Recovery. *Default setting after reset. Not Reset with a Stop Mode Recovery. * *At the XOR gate ...
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WDTMR(0F)0FH *Default setting after reset. Not Reset with a Stop Mode Recovery. Figure 45. Watchdog Timer Register ((0F) 0FH: Write Only) PS020823-0208 ® Crimzon ZLP32300 Product Specification WDT TAP INT RC OSC ...
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Standard Control Registers The standard control registers are displayed in R246 P2M(F6H *Default setting after reset. Not Reset with a Stop Mode Recovery. Figure 46. Port 2 Mode Register (F6H: Write Only) R247 P3M(F7H ...
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R248 P01M(F8H *Default setting after reset; only P00, P01 and P07 are available on Crimzon ZLP32300 20-pin con- figurations. Figure 48. Port 0 and 1 Mode Register (F8H: Write Only) PS020823-0208 ® ...
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R249 IPR(F9H Figure 49. Interrupt Priority Register (F9H: Write Only) PS020823-0208 ® Crimzon ZLP32300 Product Specification Interrupt Group Priority 000 Reserved 001 C > A > B 010 A > B >C ...
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R250 IRQ(FAH Figure 50. Interrupt Request Register (FAH: Read/Write) R251 IMR(FBH *Default setting after reset * *Only by using EI, DI instruction required before changing the IMR register Figure 51. Interrupt Mask ...
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R252 Flags(FCH Figure 52. Flag Register (FCH: Read/Write) R253 RP(FDH Default setting after reset = 0000 0000 Figure 53. Register Pointer (FDH: Read/Write) PS020823-0208 ...
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R254 SPH(FEH Figure 54. Stack Pointer High (FEH: Read/Write) R255 SPL(FFH Figure 55. Stack Pointer Low (FFH: Read/Write) PS020823-0208 ® Crimzon ZLP32300 Product Specification ...
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Electrical Characteristics Absolute Maximum Ratings Stresses greater than those listed in This rating is a stress rating only. Functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure ...
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Capacitance Table 18 lists the capacitances. Table 18. Capacitance Parameter Input capacitance Output capacitance I/O capacitance ° GND = 1.0 MHz, unmeasured A CC pins returned to GND DC Characteristics Table ...
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Table 19. DC Characteristics (Continued) Symbol Parameter V I Input Leakage 2.0-3 Pull-Up Resistance 2.0 PU 3.6 I Output Leakage 2.0-3 Supply Current 2.0 CC 3.6 I Standby Current 2.0 CC1 (HALT Mode) 3.6 I Standby ...
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AC Characteristics Figure 57 and Table 20 Clock IRQ N Clock Setup Stop Mode Recovery Source PS020823-0208 describe the Alternating Current (AC) characteristics Figure 57. AC Timing ...
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Table 20. AC Characteristics No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise and Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer ...
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Packaging Package information for all versions of Crimzon ZLP32300 is displayed in through Figure 65. Figure 58. 20-Pin PDIP Package Diagram PS020823-0208 ® Crimzon ZLP32300 Product Specification 80 Figure 58 Packaging ...
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Figure 59. 20-Pin SOIC Package Diagram PS020823-0208 ® Crimzon ZLP32300 Product Specification 81 Packaging ...
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Figure 60. 20-Pin SSOP Package Diagram PS020823-0208 ® Crimzon ZLP32300 Product Specification 82 Packaging ...
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Figure 61. 28-Pin SOIC Package Diagram PS020823-0208 ® Crimzon ZLP32300 Product Specification 83 Packaging ...
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Figure 62. 28-Pin PDIP Package Diagram PS020823-0208 ® Crimzon ZLP32300 Product Specification 84 Packaging ...
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DETAIL SEATING PLANE Figure 63. 28-Pin SSOP Package Diagram Figure 64. 40-Pin PDIP Package Diagram PS020823-0208 C MILLIMETER SYMBOL MIN NOM A 1.73 1.86 A1 0.05 0. ...
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... Detail A Figure 65. 48-Pin SSOP Package Design ® Contact Zilog on the actual bonding diagram and coordinate for chip-on-board assem- Note: bly. PS020823-0208 Detail SEATING PLANE L 0-8˚ ® Crimzon ZLP32300 Product Specification CONTROLLING DIMENSIONS : MM LEADS ARE COPLANAR WITHIN .004 INCH Packaging 86 ...
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... Ordering Information The Crimzon ZLP32300 is available for the following parts: Device Crimzon ZLP32300 PS020823-0208 Part Number Description ZLP32300H4832G 48-pin SSOP 32 K OTP ZLP32300P4032G 40-pin PDIP 32 K OTP ZLP32300H2832G 28-pin SSOP 32 K OTP ZLP32300P2832G 28-pin PDIP 32 K OTP ZLP32300S2832G 28-pin SOIC 32 K OTP ...
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... Device Notes 1. Replace C with G for Lead-Free Packaging. 2. Contact www.zilog.com For fast results, contact your local Zilog desired. PS020823-0208 Part Number Description ZLP32300P2008G 20-pin PDIP 8 K OTP ZLP32300S2008G 20-pin SOIC 8 K OTP ZLP32300H4804G 48-pin SSOP 4 K OTP ZLP32300P4004G 40-pin PDIP 4 K OTP ...
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... KB of OTP and built with lead-free solder 32300 PS020823-0208 Crimzon Product Specification Environmental Flow G = Lead Free Memory Size Number of Pins in Package Pins Pins Pins Pins Package Type H = SSOP P = PDIP S = SOIC Product Number 32300 Product Line Crimzon ZLP32300 OTP Zilog Product Prefix ® ZLP32300 89 Ordering Information ...
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PS020823-0208 ® Crimzon ZLP32300 Product Specification 90 Ordering Information ...
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Index Numerics 16-bit counter/timer circuits 40 20-pin DIP package diagram 80 20-pin SSOP package diagram 82 28-pin DIP package diagram 84 28-pin SOIC package diagram 83 28-pin SSOP package diagram 85 40-pin DIP package diagram 85 48-pin SSOP package diagram ...
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T8 37 description functional 19 general 3 pin 5 E EPROM selectable options 58 expanded register file 20 expanded register file architecture 22 expanded register file control registers 64 flag 73 interrupt mask register 72 interrupt priority register 71 interrupt ...
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O oscillator configuration 46 output circuit, counter/timer 43 P package information 20-pin DIP package diagram 80 20-pin SSOP package diagram 82 28-pin DIP package diagram 84 28-pin SOIC package diagram 83 28-pin SSOP package diagram 85 40-pin DIP package diagram ...
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Counter/Timer2 LS-Byte Hold 26 Counter/Timer2 MS-Byte Hold 26 Counter/Timer8 Control 27 Counter/Timer8 High Hold 27 Counter/Timer8 Low Hold 27 CTR2 Counter/Timer 16 Control 31 CTR3 T8/T16 Control 33 Stop Mode Recovery2 33 T16_Capture_LO 26 T8 and T16 Common ...
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... For answers to technical questions about the product, documentation, or any other issues with Zilog’s offerings, please visit Zilog’s Knowledge Base at http://www.zilog.com/kb. For any comments, detail technical questions, or reporting problems, please visit Zilog’s Technical Support at http://support.zilog.com. PS020823-0208 ® ...