Z8F012AHH020SG Zilog, Z8F012AHH020SG Datasheet

IC ENCORE XP MCU FLASH 1K 20SSOP

Z8F012AHH020SG

Manufacturer Part Number
Z8F012AHH020SG
Description
IC ENCORE XP MCU FLASH 1K 20SSOP
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet

Specifications of Z8F012AHH020SG

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
1KB (1K x 8)
Program Memory Type
FLASH
Eeprom Size
16 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4029
Z8F012AHH020SG
High-Performance 8-Bit Microcontrollers
Z8 Encore! XP
®
F082A
Series
Product Specification
PS022825-0908
®
Copyright ©2008 by Zilog
, Inc. All rights reserved.
www.zilog.com

Related parts for Z8F012AHH020SG

Z8F012AHH020SG Summary of contents

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... High-Performance 8-Bit Microcontrollers Z8 Encore! XP Series Product Specification PS022825-0908 ® Copyright ©2008 by Zilog , Inc. All rights reserved. www.zilog.com ® F082A ...

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... TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, and Z8 Encore! XP are registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. ...

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Revision History Each instance in Revision History reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appropriate links in the table below. Revision Date Level September 25 2008 May 2008 ...

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Table of Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Reset, Stop Mode Recovery, and Low Voltage Detection . . . . . . . . . . . . . . 23 Reset Types . . . . . . . . . . . . . . . ...

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Port A–C Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ...

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Watchdog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Watchdog Timer Reload Unlock Sequence . ...

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Hardware Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Trim Bit Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Trim Bit Address 0002H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Trim Bit Address 0003H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Trim Bit Address 0004H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Zilog Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 ADC Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Temperature Sensor Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Watchdog Timer Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Serialization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Randomized Lot Identifier ...

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OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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General Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 236 On-Chip Debugger Timing . . . . . ...

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... Two enhanced 16-bit timers with capture, compare, and PWM capability • Watchdog Timer (WDT) with dedicated internal RC oscillator • vectored interrupts • I/O pins depending upon package PS022825-0908 ® MCU family of products are the first in a line of Zilog ® Z8 Encore! XP F082A Series Product Specification ® microcon- ® F082A Series ® ...

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Up to thirteen 5 V-tolerant input pins • ports capable of direct LED drive with no current limit resistor required • On-Chip Debugger (OCD) • Voltage Brownout (VBO) protection • Programmable low battery detection (LVD) (8-pin ...

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Table 1. Z8 Encore! XP F082A Series Family Part Selection Guide Part Flash RAM NVDS Number (KB) (B) Z8F082A 8 1024 Z8F081A 8 1024 Z8F042A 4 1024 128 Z8F041A 4 1024 128 Z8F022A 2 512 Z8F021A 2 512 Z8F012A ...

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Block Diagram Figure 1 displays the block diagram of the architecture of the Z8 Encore! XP Series devices. eZ8 CPU Memory Busses Register Bus Timers UART Comparator IrDA GPIO Figure 1. Z8 Encore! XP F082A Series Block Diagram PS022825-0908 System ...

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... CPU and Peripheral Overview eZ8 CPU Features The eZ8 CPU, Zilog’s latest 8-bit Central Processing Unit (CPU), meets the continuing demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a superset of the original Z8 • Direct register-to-register architecture allows each register to function as an accumulator, improving execution time and decreasing the required program memory ...

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Low-Power Operational Amplifier The optional low-power operational amplifier (LPO general-purpose amplifier primarily targeted for current sense applications. The LPO output may be routed internally to the ADC or externally to a pin. Internal Precision Oscillator The internal precision ...

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Universal Asynchronous Receiver/Transmitter The full-duplex universal asynchronous receiver/transmitter (UART) is included in all Z8 Encore! XP package types. The UART supports 8- and 9-bit data modes and selectable parity. The UART also supports multi-drop address processing in hardware. The UART ...

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Interrupt Controller The Z8 Encore! XP interrupts consist of 8 internal peripheral interrupts and 12 general-purpose I/O pin interrupt sources. The interrupts have three levels of programmable interrupt priority. Reset Controller The Z8 Encore! XP F082A Series products can be ...

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Pin Description The Z8 Encore! XP and pin configurations. This chapter describes the signals and available pin configurations for each of the package styles. For information on physical package specifications, see Packaging on page 241. Available Packages The following package ...

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The pin configurations listed are preliminary and subject to change based on manufacturing limitations. PA0/T0IN/T0OUT/XIN//DBG PA1/T0OUT/XOUT/ANA3/VREF/CLKIN PA2/RESET/DE0/T1OUT Figure 2. Z8F08xA, Z8F04xA, Z8F02xA, and Z8F01xA in 8-Pin SOIC, QFN/MLF-S, or PDIP Package PB1/ANA1/AMPINN PB2/ANA2/AMPINP PB3/CLKIN/ANA3 PA0/T0IN/T0OUT/XIN PA1/T0OUT/XOUT PA2/DE0 PA3/CTS0 PA4/RXD0 Figure ...

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Signal Descriptions Table 2 describes the Z8 Encore! XP F082A Series signals. See page 9 to determine the signals available for the specific package styles. Table 2. Signal Descriptions I/O Signal Mnemonic Description General-Purpose I/O Ports A–D PA[7:0] I/O Port ...

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Table 2. Signal Descriptions (Continued) I/O Signal Mnemonic Description Analog ANA[7:0] I Analog Port. These signals are used as inputs to the analog-to-digital converter (ADC). VREF I/O Analog-to-digital converter reference voltage input, or buffered output for internal reference. Low-Power Operational ...

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Table 2. Signal Descriptions (Continued) I/O Signal Mnemonic Description Power Supply V I Digital Power Supply Analog Power Supply Digital Ground Analog Ground. SS Note: The AV and AV signals are ...

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Table 3. Pin Characteristics (20- and 28-pin Devices) (Continued) Symbol Reset Mnemonic Direction Direction PC[7:0] I/O I RESET/PD0 I/O I/O (defaults to RESET) VDD N/A N/A VSS N/A N/A PB6 and PB7 are available only in those devices without ADC. ...

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... The Data Memory contains addresses for all memory locations that contain data only. These three address spaces are covered briefly in the following subsections. For more information on eZ8 CPU and its address space, refer to eZ8 CPU Core User Manual (UM0128) available for download at www.zilog.com. Register File The Register File address space in the Z8 Encore! Register File is composed of two sections: control registers and general-purpose registers ...

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Flash memory addresses returns unimplemented Program Memory addresses produces no effect. Program Memory Maps for the Z8 Encore! XP F082A Series products. Table 5. Z8 Encore! XP F082A Series Program Memory Maps Program Memory Address (Hex) ...

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Table 5. Z8 Encore! XP F082A Series Program Memory Maps (Continued) Program Memory Address (Hex) Z8F022A and Z8F021A Products 0000–0001 0002–0003 0004–0005 0006–0007 0008–0037 0038–0039 003A–003D 003E–07FF Z8F012A and Z8F011A Products 0000–0001 0002–0003 0004–0005 0006–0007 0008–0037 0038–0039 003A–003D 003E–03FF Table ...

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... Program Memory Address (Hex) Function FE00–FE3F FE40–FE53 FE54–FE5F FE60–FE7F FE80–FFFF PS022825-0908 Z8 Encore! XP Product Specification Zilog Option Bits/Calibration Data Part Number 20-character ASCII alphanumeric code Left justified and filled with FFH Reserved Zilog Calibration Data Reserved ® F082A Series ...

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Register Map Table 7 provides the address map for the Register File of the Z8 Encore! XP Series devices. Not all devices and package styles in the Z8 Encore! XP F082A Series support the ADC, or all of the GPIO ...

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Table 7. Register File Address Map (Continued) Address (Hex) Register Description F0B Timer 1 Reload Low Byte F0C Timer 1 PWM High Byte F0D Timer 1 PWM Low Byte F0E Timer 1 Control 0 F0F Timer 1 Control 1 F10–F6F ...

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Table 7. Register File Address Map (Continued) Address (Hex) Register Description F91–FBF Reserved Interrupt Controller FC0 Interrupt Request 0 FC1 IRQ0 Enable High Bit FC2 IRQ0 Enable Low Bit FC3 Interrupt Request 1 FC4 IRQ1 Enable High Bit FC5 IRQ1 ...

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Table 7. Register File Address Map (Continued) Address (Hex) Register Description FDF Port D Output Data FE0–FEF Reserved Watchdog Timer (WDT) FF0 Reset Status (Read-only) Watchdog Timer Control (Write-only) FF1 Watchdog Timer Reload Upper Byte FF2 Watchdog Timer Reload High ...

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Reset, Stop Mode Recovery, and Low Voltage Detection The Reset Controller within the Z8 Encore! XP Mode Recovery operation and provides indication of low supply voltage conditions. In typical operation, the following events cause a Reset: • Power-On Reset (POR) ...

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Table 8. Reset and Stop Mode Recovery Characteristics and Latency Reset Type Control Registers System Reset Reset (as applicable) System Reset with Crystal Reset (as applicable) Oscillator Enabled Stop Mode Recovery Unaffected, except WDT_CTL and OSC_CTL registers Stop Mode Recovery ...

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Reset Sources Table 9 lists the possible sources of a system reset. Table 9. Reset Sources and Resulting Reset Type Operating Mode Reset Source NORMAL or HALT Power-On Reset/Voltage modes Brownout Watchdog Timer time-out when configured for Reset RESET pin ...

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V POR V VBO Internal Precision Oscillator Crystal Oscillator Internal RESET signal Note: Not to Scale Figure 5. Power-On Reset Operation Voltage Brownout Reset The devices in the Z8 Encore! XP F082A Series provide low ...

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VCC = 3 POR V VBO Program Execution System Clock Internal RESET signal Note: Not to Scale Figure 6. Voltage Brownout Reset Operation The POR level is greater than the VBO level by the specified hysteresis value. This ...

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A reset pulse three clock cycles in duration might trigger a reset; a pulse four cycles in duration always triggers a reset. While the RESET input pin is asserted Low, the Z8 Encore! XP remain ...

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Following Stop Mode Recovery, the STOP bit in the Reset Status (RSTSTAT) Register is set to 1. ing actions. The text following provides more detailed information about each of the Stop Mode Recovery sources. Table 10. Stop Mode ...

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Stop Mode Recovery without being written to the Port Input Data register or without initiating an interrupt (if enabled for that pin). Stop Mode Recovery Using the External RESET Pin When the Z8 Encore! XP F082A Series device is ...

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Table 11. Reset Status Register (RSTSTAT BITS POR STOP FIELD See descriptions below RESET R R R/W ADDR Reset or Stop Mode Recovery Event Power-On Reset Reset using RESET pin assertion Reset using Watchdog Timer time-out Reset using ...

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PS022825-0908 Z8 Encore! XP Product Specification Reset, Stop Mode Recovery, and Low Voltage Detection ® F082A Series 32 ...

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Low-Power Modes The Z8 Encore! XP F082A Series products contain power-saving features. The highest level of power reduction is provided by the STOP mode, in which nearly all device functions are powered down. The next lower level of power reduction ...

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HALT Mode Executing the eZ8 CPU’s HALT instruction places the device into HALT mode, which powers down the CPU but leaves all other peripherals active. In HALT mode, the operating characteristics are: • Primary oscillator is enabled and continues to ...

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OFF. To use the LPO, clear the LPO bit, turning it ON. Clearing this bit might interfere with normal ADC measurements on ANA0 (the LPO out- put). This bit enables the amplifier even in STOP mode. ...

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PS022825-0908 ® Z8 Encore! XP F082A Series Product Specification Low-Power Modes 36 ...

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General-Purpose Input/Output The Z8 Encore for general-purpose input/output (GPIO) operations. Each port contains control and data registers. The GPIO control registers determine data direction, open-drain, output drive current, programmable pull-ups, Stop Mode Recovery functional- ity, and alternate pin ...

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Architecture Figure 7 displays a simplified block diagram of a GPIO port pin. In this figure, the ability to accommodate alternate functions and variable port current drive strength is not displayed. System Port Output Data Register DATA D Q Bus ...

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PA0 and PA6 contain two different timer functions, a timer input and a complementary timer output. Both of these functions require the same GPIO configuration, the selection between the two is based on the timer mode. See Caution: For pin ...

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GPIO pin not present, the debug feature is disabled until/unless another reset event occurs. For more details, see Crystal Oscillator Override For systems using a crystal oscillator, PA0 and PA1 are used to connect ...

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Table 14. Port Alternate Function Mapping (Non 8-Pin Parts) Port Pin Mnemonic PA0 T0IN/T0OUT* Port A Reserved PA1 T0OUT Reserved PA2 DE0 Reserved PA3 CTS0 Reserved PA4 RXD0/IRRX0 Reserved PA5 TXD0/IRTX0 Reserved PA6 T1IN/T1OUT* Reserved PA7 T1OUT Reserved Note: Because ...

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Table 14. Port Alternate Function Mapping (Non 8-Pin Parts) (Continued) Port Pin Mnemonic PB0 Reserved Port B ANA0/AMPOUT PB1 Reserved ANA1/AMPINN PB2 Reserved ANA2/AMPINP PB3 CLKIN ANA3 PB4 Reserved ANA7 PB5 Reserved VREF* PB6 Reserved Reserved PB7 Reserved Reserved Note: ...

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Table 14. Port Alternate Function Mapping (Non 8-Pin Parts) (Continued) Port Pin Mnemonic PC0 Reserved Port C ANA4/CINP/LED Drive PC1 Reserved ANA5/CINN/ LED Drive PC2 Reserved ANA6/LED/ VREF* PC3 COUT LED PC4 Reserved LED PC5 Reserved LED PC6 Reserved LED ...

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Table 15. Port Alternate Function Mapping (8-Pin Parts) Port Pin Mnemonic PA0 T0IN Port A Reserved Reserved T0OUT PA1 T0OUT Reserved CLKIN Analog Functions* ADC Analog Input/VREF PA2 DE0 RESET T1OUT Reserved PA3 CTS0 COUT T1IN Analog Functions* ADC Analog ...

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GPIO Interrupts Many of the GPIO port pins can be used as interrupt sources. Some port pins can be con- figured to generate an interrupt request on either the rising edge or falling edge of the pin input signal. Other ...

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Port A–D Address Registers The Port A–D Address registers select the GPIO Port functionality accessible through the Port A–D Control registers. The Port A–D Address and Control registers combine to pro- vide access to all GPIO Port controls Table 17. ...

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Table 18. Port A–D Control Registers (PxCTL BITS FIELD RESET R/W R/W R/W ADDR PCTL[7:0]—Port Control The Port Control register provides access to all sub-registers that configure the GPIO Port operation. Port A–D Data Direction Sub-Registers The Port ...

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Set 1 Sub-Registers Alternate Function Set 2 Sub-Registers page 38 to determine the alternate function associated with each port pin. Caution: Do not enable alternate functions for GPIO port pins for which there is no associated alternate function. Failure to ...

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The source current for the associated pin is disabled (open-drain mode). Port A–D High Drive Enable Sub-Registers The Port A–D High Drive Enable sub-register A–D Control register by writing the Port A–D High Drive Enable ...

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STOP mode do not initiate Stop Mode Recovery The Port pin is configured as a Stop Mode Recovery source. Any logic transition on this pin during STOP mode initiates Stop Mode Recovery. Port A–D Pull-up Enable Sub-Registers ...

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PAFS1[7:0]—Port Alternate Function Set Port Alternate Function selected as defined Port Alternate Function selected as defined in Port A–D Alternate Function Set 2 Sub-Registers The Port A–D Alternate Function Set 2 sub-register Port A–D ...

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PIN[7:0]—Port Input Data Sampled data from the corresponding port pin input Input data is logical 0 (Low Input data is logical 1 (High). Port A–D Output Data Register The Port A–D Output Data register Table 28. ...

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LEDEN[7:0]—LED Drive Enable These bits determine which Port C pins are connected to an internal current sink Tristate the Port C pin. 1= Enable controlled current sink on the Port C pin. LED Drive Level High Register The ...

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Table 31. LED Drive Level Low Register (LEDLVLL BITS FIELD 0 0 RESET R/W R/W R/W ADDR LEDLVLL[7:0]—LED Level Low Bit {LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each Port C pin ...

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... The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the interrupt controller has no effect on operation. For more information on interrupt ser- vicing by the eZ8 CPU, refer to eZ8 CPU Core User Manual (UM0128) available for download at www.zilog.com. Interrupt Vector Listing Table 32 on page 56 lists all of the interrupts available in order of priority ...

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Table 32. Trap and Interrupt Vectors in Order of Priority Program Memory Priority Vector Address Interrupt or Trap Source Highest 0002H Reset (not an interrupt) 0004H Watchdog Timer (see 003AH Primary Oscillator Fail Trap (not an interrupt) 003CH Watchdog Oscillator ...

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Table 32. Trap and Interrupt Vectors in Order of Priority (Continued) Program Memory Priority Vector Address Interrupt or Trap Source 0034H Port C Pin 1, both input edges Lowest 0036H Port C Pin 0, both input edges 0038H Reserved Architecture ...

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Interrupts are globally enabled by any of the following actions: • Execution (Enable Interrupt) instruction • Execution of an IRET (Return from Interrupt) instruction • Writing the IRQE bit in the Interrupt Control register ...

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The following coding style that clears bits in the Interrupt Request registers is not Caution: recommended. All incoming interrupts received between execution of the first mand and the final LDX command are lost. Poor coding style that can result in ...

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To avoid re-triggerings of the Watchdog Timer interrupt after exiting the associated Caution: interrupt service routine recommended that the service routine continues to read from the RSTSTAT register until the WDT bit is cleared as given in the ...

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U0RXI—UART 0 Receiver Interrupt Request interrupt request is pending for the UART 0 receiver interrupt request from the UART 0 receiver is awaiting service. U0TXI—UART 0 Transmitter Interrupt Request interrupt request ...

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Interrupt Request 2 Register The Interrupt Request 2 (IRQ2) register tored and polled interrupts. When a request is presented to the interrupt controller, the cor- responding bit in the IRQ2 register becomes 1. If interrupts are globally enabled (vectored interrupts), ...

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Table 37. IRQ0 Enable High Bit Register (IRQ0ENH) BITS 7 6 Reserved T1ENH FIELD 0 0 RESET R/W R/W R/W ADDR Reserved—Must be 0. T1ENH—Timer 1 Interrupt Request Enable High Bit T0ENH—Timer 0 Interrupt Request Enable High Bit U0RENH—UART 0 ...

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Table 39. IRQ1 Enable and Priority Encoding IRQ1ENH[x] IRQ1ENL[x] Priority where x indicates the register bits from 0–7. Table 40. IRQ1 Enable High Bit Register (IRQ1ENH) BITS 7 6 PA7VENH PA6CENH PA5ENH ...

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IRQ2 Enable High and Low Bit Registers Table 42 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit registers (Table 43 Interrupt Request 2 register. Table 42. IRQ2 Enable and Priority Encoding IRQ2ENH[x] IRQ2ENL[x] Priority 0 ...

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Reserved—Must be 0. C3ENL—Port C3 Interrupt Request Enable Low Bit C2ENL—Port C2 Interrupt Request Enable Low Bit C1ENL—Port C1 Interrupt Request Enable Low Bit C0ENL—Port C0 Interrupt Request Enable Low Bit Interrupt Edge Select Register The Interrupt Edge Select (IRQES) ...

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Table 46. Shared Interrupt Select Register (IRQSS) BITS 7 6 PA7VS PA6CS FIELD 0 0 RESET R/W R/W R/W ADDR PA7VS—PA7/LVD Selection 0 = PA7 is used for the interrupt for PA7VS interrupt request The LVD is used ...

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PS022825-0908 ® Z8 Encore! XP F082A Series Product Specification Interrupt Controller 68 ...

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Timers These Z8 Encore! XP can be used for timing, event counting, or generation of pulse-width modulated (PWM) signals. The timers’ feature include: • 16-bit reload counter. • Programmable prescaler with prescale values from 1 to 128. • PWM output ...

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Data Bus Block Control System Clock Timer Input Gate Input Capture Input Operation The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value into the Timer Reload High and Low Byte registers and setting the prescale ...

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Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state for one system clock cycle (from Low to High or from High to Low) upon timer Reload appropriate to have the Timer ...

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Set the prescale value. – If using the Timer Output alternate function, set the initial output level (High or – Low). 2. Write to the Timer High and Low Byte registers to set the starting count value (usually 0001H). This ...

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Follow the steps below for configuring a timer for COUNTER mode and initiating the count: 1. Write to the Timer Control register to: Disable the timer. – Configure the timer for COUNTER mode. – Select either the rising edge or ...

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Follow the steps below for configuring a timer for COMPARATOR COUNTER mode and initiating the count: 1. Write to the Timer Control register to: Disable the timer. – Configure the timer for COMPARATOR COUNTER mode. – Select either the rising ...

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If the TPOL bit in the Timer Control register is set to 0, the Timer Output signal begins as a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The Timer Output signal ...

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PWM DUAL OUTPUT Mode In PWM DUAL OUTPUT mode, the timer outputs a Pulse-Width Modulated (PWM) output signal pair (basic PWM signal and its complement) through two GPIO Port pins. The timer input is the system clock. The timer first ...

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PWM signal (as defined by the difference between the PWM registers and the Timer Reload registers). 5. Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM ...

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Follow the steps below for configuring a timer for CAPTURE mode and initiating the count: 1. Write to the Timer Control register to: Disable the timer. – Configure the timer for CAPTURE mode. – Set the prescale value. – Set ...

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The INPCAP bit in TxCTL0 register is cleared to indicate 0001H the timer interrupt is not caused by an input capture event. Follow the steps below for configuring a timer for CAPTURE RESTART mode and initi- ating ...

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Follow the steps below for configuring a timer for COMPARE mode and initiating the count: 1. Write to the Timer Control register to: Disable the timer. – Configure the timer for COMPARE mode. – Set the prescale value. – Set ...

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Write to the Timer High and Low Byte registers to set the starting count value. Writing these registers only affects the first pass in GATED mode. After the first timer reset in GATED mode, counting always begins at the ...

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Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing to the relevant interrupt registers.By default, the timer interrupt are generated for both input capture and reload events. If appropriate, configure the timer interrupt to ...

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Timer Control Register Definitions Timer 0–1 Control Registers Time 0–1 Control Register 0 The Timer Control Register 0 (TxCTL0) and Timer Control Register 1 (TxCTL1) deter- mine the timer operating mode band delay, two bits to configure timer interrupt definition, ...

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INPCAP—Input Capture Event This bit indicates if the most recent timer interrupt is caused by a Timer Input Capture Event Previous timer interrupt is not a result of ...

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PWM SINGLE OUTPUT mode 0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM count match and forced Low (0) upon Reload Timer Output ...

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CAPTURE RESTART mode 0 = Count is captured on the rising edge of the Timer Input signal Count is captured on the falling edge of the Timer Input signal. COMPARATOR COUNTER mode When the timer is disabled, the ...

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PWM DUAL OUTPUT mode 1001 = CAPTURE RESTART mode 1010 = COMPARATOR COUNTER mode Timer 0–1 High and Low Byte Registers The Timer 0–1 High and Low Byte (TxH and TxL) registers contain the current 16-bit timer count ...

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Timer Reload Low Byte register occurs, the temporary holding register value is written to the Timer High Byte register. This operation allows simultaneous updates of the 16-bit Timer Reload value. In COMPARE mode, the Timer Reload High and Low Byte ...

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Table 55. Timer 0–1 PWM Low Byte Register (TxPWML) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W ADDR PWMH and PWML—Pulse-Width Modulator High and Low Bytes These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared ...

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PS022825-0908 ® Z8 Encore! XP F082A Series Product Specification Timers 90 ...

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Watchdog Timer The Watchdog Timer (WDT) protects against corrupt or unreliable software, power faults, and other system-level problems which may place the Z8 Encore! XP devices into unsuitable operating states. The features of Watchdog Timer include: • On-chip RC oscillator. ...

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Watchdog Timer Refresh When first enabled, the Watchdog Timer is loaded with the value in the Watchdog Timer Reload registers. The Watchdog Timer counts down to instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes the ...

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WDT Reset in Normal Operation If configured to generate a Reset when a time-out occurs, the Watchdog Timer forces the device into the System Reset state. The WDT status bit in the Reset Status (RSTSTAT) register is set to 1. ...

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Watchdog Timer Reload Registers results in a one-second timeout at room temperature and 3.3 V supply voltage. Timeouts other than one second may be obtained by scaling the calibration values up or down as required. Note: The Watchdog Timer accuracy ...

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The 24-bit WDT Reload Value must not be set to a value less than Caution: Table 58. Watchdog Timer Reload Upper Byte Register (WDTU) BITS 7 6 FIELD RESET R/W ADDR R/W* - Read returns the current WDT count value. ...

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PS022825-0908 ® Z8 Encore! XP F082A Series Product Specification Watchdog Timer 96 ...

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Universal Asynchronous Receiver/Transmitter The universal asynchronous receiver/transmitter (UART full-duplex communication channel capable of handling asynchronous data transfers. The UART uses a single 8-bit data mode with selectable parity. Features of the UART include: • 8-bit asynchronous data transfer. ...

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Parity Checker RXD Receive Shifter Receive Data Register System Bus Transmit Data Register Transmit Shift TXD Register Parity Generator CTS DE Operation Data Format The UART always transmits and receives data in an 8-bit data format, least-significant bit first. An ...

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Idle State of Line lsb 1 Start Bit0 0 Figure 11. UART Asynchronous Data Format without Parity Idle State of Line lsb 1 Start Bit0 Bit1 0 Figure 12. UART Asynchronous Data Format with Parity Transmitting Data using the Polled ...

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Check the TDRE bit in the UART Status 0 register to determine if the Transmit Data register is empty (indicated by a 1). If empty, continue to register is full (indicated by a 0), continue to monitor the TDRE ...

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The UART is now configured for interrupt-driven data transmission. Because the UART Transmit Data register is empty, an interrupt is generated immediately. When the UART Transmit interrupt is detected, the associated interrupt service routine (ISR) performs the following: 1. Write ...

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Receiving Data using the Interrupt-Driven Method The UART Receiver interrupt indicates the availability of new data (as well as error conditions). Follow the steps below to configure the UART receiver for interrupt-driven operation: 1. Write to the UART Baud Rate ...

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Clears the UART Receiver interrupt in the applicable Interrupt Request register. 4. Executes the IRET instruction to return from the interrupt-service routine and await more data. Clear To Send (CTS) Operation The CTS pin, if enabled by the CTSE ...

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In general, the address compare feature reduces the load on the CPU, because it does not require access to the UART when it receives data directed to other devices on the multi-node network. The following three MULTIPROCESSOR modes ...

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Driver Enable is an active High signal that envelopes the entire transmitted data frame including parity and Stop bits as displayed in when a byte is written to the UART Transmit Data register. The Driver Enable signal asserts at least ...

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This action provides 7 bit periods of latency to load the Transmit Data register before the Transmit shift register completes shifting the current character. Writing to the UART Transmit Data register clears the TDRE bit to 0. Receiver Interrupts ...

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Read Data Figure 15. UART Receiver Interrupt Service Routine Flow Baud Rate Generator Interrupts If the baud rate generator (BRG) interrupt enable is set, the UART Receiver interrupt asserts when the UART Baud Rate Generator reloads. This condition allows the ...

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UART. The UART data rate is calculated using the following equation: UART Data Rate (bits/s) When the UART is disabled, the Baud Rate Generator functions as a basic 16-bit ...

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CTSE bit. If the CTS signal is Low and the CTSE bit is 1, the transmitter is enabled Transmitter disabled Transmitter enabled. REN—Receive Enable This bit enables or disables the receiver Receiver ...

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MPMD[1:0]—MULTIPROCESSOR Mode If MULTIPROCESSOR (9-bit) mode is enabled The UART generates an interrupt request on all received bytes (data and address The UART generates an interrupt request only on received address bytes The UART ...

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Received data does not generate an interrupt request to the Interrupt Controller. Only receiver errors generate an interrupt request. IREN—Infrared Encoder/Decoder Enable 0 = Infrared Encoder/Decoder is disabled. UART operates normally Infrared Encoder/Decoder is enabled. The ...

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No framing error occurred framing error occurred. BRKD—Break Detect This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit, and Stop bit(s) are all 0s this bit is set to 1. Reading ...

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MPRX—Multiprocessor Receive Returns the value of the most recent multiprocessor bit received. Reading from the UART Receive Data register resets this bit to 0. UART Transmit Data Register Data bytes written to the UART Transmit Data (UxTXD) register out on ...

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UART Address Compare Register The UART Address Compare (UxADDR) register stores the multi-node network address of the UART (see all incoming address bytes are compared to the value stored in the Address Compare register. Receive interrupts and RDA assertions only ...

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The UART data rate is calculated using the following equation: UART Baud Rate (bits/s) For a given UART data rate, calculate the integer baud rate divisor value using the follow- ing equation: UART Baud Rate Divisor Value (BRG) The baud ...

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Table 70. UART Baud Rates (Continued) 3.579545 MHz System Clock Acceptable BRG Divisor Actual Rate Rate (kHz) (Decimal) 1250.0 N/A 625.0 N/A 250.0 1 223.72 115.2 2 57.6 4 38.4 6 19.2 12 9.60 23 4.80 47 2.40 93 1.20 ...

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Infrared Encoder/Decoder The Z8 Encore! XP high-performance UART to Infrared Encoder/Decoder (Endec). The Infrared Endec is integrated with an on-chip UART to allow easy communication between the Z8 Encore! and IrDA Physical Layer Specification, Version 1.3-compliant infrared transceivers. Infrared communication ...

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Endec, and passed to the UART. Communication is half-duplex, which means simultaneous data transmission and reception is not allowed. The baud rate is set by the UART’s Baud Rate Generator and supports IrDA standard baud rates from 9600 baud to ...

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Receiving IrDA Data Data received from the infrared transceiver using the IR_RXD signal through the RXD pin is decoded by the Infrared Endec and passed to the UART. The UART’s baud rate clock is used by the Infrared Endec to ...

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If an incoming pulse is detected inside this window this process is repeated. If the incoming data is a logical 1 (no pulse), ...

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Analog-to-Digital Converter The analog-to-digital converter (ADC) converts an analog input signal to its digital repre- sentation. The features of this sigma-delta ADC include: • 11-bit resolution in DIFFERENTIAL mode. • 10-bit resolution in SINGLE-ENDED mode. • Eight single-ended analog input ...

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Internal Voltage Vrefsel Reference Generator Ref Input 13 ADC Data 13 bit Sigma-Delta ADC Analog In - Analog In + ADC IRQ BUFFMODE Figure 19. Analog-to-Digital Converter Block Diagram Operation Data Format In both SINGLE-ENDED and DIFFERENTIAL modes, the ...

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In SINGLE-ENDED mode, the output generally ranges from 0 to +1023, but offset errors can cause small negative values. The ADC registers actually return 13 bits of data, ...

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If the internal voltage reference must be output to a pin, set the – 1. The internal voltage reference must be enabled in this case. Write the – voltage reference level or to disable the internal reference. The contained in ...

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Write to the ADC Control Register 0 The bit fields in the ADC Control register may be written simultaneously: Write to the – sources (different input pins available depending on the device). Set CONT select continuous ...

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... ADC uncomp OFFCAL ) ( ( – Otherwise, the second term incorrectly evaluates to zero. ® Z8 Encore! XP F082A Series Product Specification Zilog Table 135 on page 231). Subse- ADC Con- GAINCAL 2 ) × ) ⁄ – Analog-to-Digital Converter 126 ...

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... ADC results to be scaled by a factor of 8/7. ADC Compensation Details High efficiency assembly code that performs this compensation is available for download on www.zilog.com. The following is a bit-specific description of the ADC compensation process used by this code. The following data bit definitions are used: ...

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Compensation Steps: 1. Correct for Offset ADC MSB - Offset MSB = #1 MSB 2. Take absolute value of the offset corrected ADC value if negative—the gain correction factor is computed assuming positive numbers, with sign restoration afterward. #2 MSB ...

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MSB 6. Add the gain correction factor to the original offset corrected value. #5 MSB + #1 MSB = #6 MSB 7. Shift the result to the right, using the sign bit determined in detection of computational overflow. S-> ...

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ADC Control Register Definitions ADC Control Register 0 The ADC Control Register 0 (ADCCTL0) selects the analog input channel and initiates the analog-to-digital conversion. It also selects the voltage reference configuration. Table 71. ADC Control Register 0 (ADCCTL0) BITS 7 ...

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ANAIN[3:0]—Analog Input Select These bits select the analog input for conversion. Not all Port pins in this list are available in all packages for the Z8 Encore! XP able with each package style, see analog inputs. Usage of these bits ...

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ADC Control/Status Register 1 The ADC Control/Status Register 1 (ADCCTL1) configures the input buffer stage, enables the threshold interrupts and contains the status of both threshold triggers also used to select the voltage reference configuration. Table 72. ADC ...

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Table 73. ADC Data High Byte Register (ADCD_H) BITS 7 6 FIELD X X RESET R R R/W ADDR X = Undefined. ADCDH—ADC Data High Byte This byte contains the upper eight bits of the ADC output. These bits are ...

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Low Power Operational Amplifier Overview The LPO is a general-purpose low power operational amplifier. Each of the three ports of the amplifier is accessible from the package pins. The LPO contains only one pin configu- ration: ANA0 is the output/feedback ...

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Comparator The Z8 Encore! XP compares two analog input signals. These analog signals may be external stimulus from a pin (CINP and/or CINN) or internally generated signals. Both a programmable voltage reference and the temperature sensor output voltage are available ...

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Comparator Control Register Definitions Comparator Control Register The Comparator Control Register (CMP0) configures the comparator inputs and sets the value of the internal voltage ...

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V 1010–1111 = Reserved For 8-pin devices: 000000 = 0.00 V 000001 = 0.05 V 000010 = 0.10 V 000011 = 0.15 V 000100 = 0.20 V 000101 = 0.25 V 000110 = 0.30 V 000111 = ...

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PS022825-0908 ® Z8 Encore! XP F082A Series Product Specification Comparator 138 ...

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Temperature Sensor The on-chip Temperature Sensor allows you to measure temperature on the die with either the on-board ADC or on-board comparator. This block is factory calibrated for in-circuit software correction. Uncalibrated accuracy is significantly worse, therefore the tempera- ture ...

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Assuming a compensated ADC measurement, the following equation defines the relation- ship between the ADC reading and the die temperature: ⁄ 128 where the temperature in C; ADC is the 10-bit compensated ADC value; ...

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Flash Memory The products in the Z8 Encore! XP memory (8192 (4096 (2048 bytes (1024) with read/write/ erase capability. The Flash Memory can be programmed and erased in-circuit by user ...

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KB Flash Program Memory Addresses (hex) 1FFF Sector 7 1C00 1BFF Sector 6 1800 17FF Sector 5 1400 13FF Sector 4 1000 0FFF Sector 3 0C00 0BFF Sector 2 0800 07FF Sector 1 0400 03FF Sector 0 0000 Figure ...

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Operation The Flash Controller programs and erases Flash memory. The Flash Controller provides the proper Flash controls and timing for Byte Programming, Page Erase, and Mass Erase of Flash memory. The Flash Controller contains several protection mechanisms to prevent accidental ...

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Reset Lock State 0 Write Page Select Register Write FCTL No 73H Yes Lock State 1 Write FCTL No 8CH Yes Write Page Select Register No Page Select values match? Yes Yes Page in Protected Sector? No Page Unlocked Program/Erase ...

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Flash Operation Timing Using the Flash Frequency Registers Before performing either a program or erase operation on Flash memory, you must first configure the Flash Frequency High and Low Byte registers. The Flash Frequency registers allow programming and erasing of ...

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Table 77. Flash Code Protection Using the Flash Option Bits Flash Code Protection Description FWP 0 Programming and erasing disabled for all of Flash Program Memory. In user code programming, Page Erase, and Mass Erase are all disabled. Mass ...

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... Byte Programming can be accomplished using the On-Chip Debugger's Write Memory command or eZ8 CPU execution of the LDC or LDCI instructions. Refer to the eZ8 CPU User Manual (available for download at www.zilog.com) for a description of the LDC and LDCI instructions. While the Flash Controller programs the Flash memory, the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate ...

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... Erase operations are also supported when the Flash Controller is bypassed. For more information on bypassing the Flash Controller, refer to Third-Party Flash Pro- gramming Support for Z8 Encore! load at www.zilog.com. Flash Controller Behavior in DEBUG Mode The following changes in behavior of the Flash Controller occur when the Flash Control- ler is accessed using the On-Chip Debugger: • ...

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Flash Control Register Definitions Flash Control Register The Flash Controller must be unlocked using the Flash Control (FCTL) register before programming or erasing the Flash memory. Writing the sequence to the Flash Control register unlocks the Flash Controller. When the ...

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Flash Status Register The Flash Status (FSTAT) register indicates the current state of the Flash Controller. This register can be read at any time. The read-only Flash Status register shares its Register File address with the Write-only Flash Control register. ...

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Table 80. Flash Page Select Register (FPS) BITS 7 6 INFO_EN FIELD 0 0 RESET R/W R/W R/W ADDR INFO_EN—Information Area Enable 0 = Information Area us not selected Information Area is selected. The Information Area is mapped ...

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SPROT7-SPROT0—Sector Protection Each bit corresponds to a 512 byte Flash sector. For the Z8F08xx devices, the upper 3 bits must be zero. For the Z8F04xx devices all bits are used. For the Z8F02xx devices, the upper 4 bits are unused. ...

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Flash Option Bits Programmable Flash option bits allow user configuration of certain aspects of ® Z8 Encore! XP Flash program memory and loaded into holding registers during Reset. The features avail- able for control through the Flash Option Bits include: ...

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... Serialization Bits As an optional feature, Zilog serialized products, the individual devices are programmed with unique serial numbers. These serial numbers are binary values, four bytes in length. The numbers increase in size with each device, but gaps in the serial sequence may exist. ...

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... Randomized Lot Identification Bits As an optional feature, Zilog is able to provide a factory-programmed random lot identifier. With this feature, all devices in a given production lot are programmed with the same random number. This random number is uniquely regenerated for each successive production lot and is not likely to be repeated. ...

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Trim Bit Data Register The Trim Bid Data (TRMDR) register contains the read or write data for access to the trim option bits (Table Table 85. Trim Bit Data Register (TRMDR) BITS 7 6 FIELD 0 0 RESET R/W R/W ...

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Watchdog Timer is enabled upon execution of the WDT instruction. Once enabled, the Watchdog Timer can only be disabled by a Reset or Stop Mode Recovery. This setting is the default for unprogrammed (erased) Flash. OSC_SEL[1:0]—Oscillator Mode Selection ...

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Flash Program Memory Address 0001H Table 87. Flash Options Bits at Program Memory Address 0001H BITS 7 6 Reserved FIELD U U RESET R/W R/W R/W ADDR Note Unchanged by Reset. R/W = Read/Write. Reserved—Must be 1. XTLDIS—State ...

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Trim Bit Address 0001H Table 89. Trim Option Bits at 0001H BITS 7 6 FIELD U U RESET R/W R/W R/W ADDR Note Unchanged by Reset. R/W = Read/Write. Reserved—Altering this register may result in incorrect device operation. ...

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Reserved—Must be 1. LVD_TRIM—Low Voltage Detect Trim This trimming affects the low voltage detection threshold. Each LSB represents change in the threshold level. Alternatively, the low voltage threshold may be computed from the options bit value by ...

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... BITS 7 6 FIELD U U RESET R/W R/W R/W ADDR Note Unchanged by Reset. R/W = Read/Write. Reserved—Altering this register may result in incorrect device operation. Zilog Calibration Data ADC Calibration Data Table 93. ADC Calibration Bits BITS 7 6 FIELD U U RESET R/W R/W R/W ADDR Note Unchanged by Reset ...

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Table 94. ADC Calibration Data Location Info Page Memory Address Address Compensation Usage 60 FE60 Offset 08 FE08 Gain High Byte 09 FE09 Gain Low Byte 63 FE63 Offset 0A FE0A Gain High Byte 0B FE0B Gain Low Byte 66 ...

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Table 94. ADC Calibration Data Location (Continued) Info Page Memory Address Address Compensation Usage 34 FE34 Negative Gain High Byte 35 FE35 Negative Gain Low Byte 78 FE78 Offset 18 FE18 Positive Gain High Byte 19 FE19 Positive Gain Low ...

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Temperature Sensor Calibration Data Table 95. Temperature Sensor Calibration High Byte at 003A (TSCALH) BITS 7 6 FIELD U U RESET R/W R/W R/W ADDR Note Unchanged by Reset. R/W = Read/Write. TSCALH – Temperature Sensor Calibration High ...

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WDTCALH—Watchdog Timer Calibration High Byte The WDTCALH and WDTCALL bytes, when loaded into the Watchdog Timer reload registers result in a one second timeout at room temperature and 3.3 V supply voltage. To use the Watchdog Timer calibration, user code ...

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Table 100. Serialization Data Locations Info Page Address Randomized Lot Identifier Table 101. Lot Identification Number (RAND_LOT) BITS 7 6 FIELD U U RESET R/W R/W R/W ADDR Note Unchanged by Reset. R/W = ...

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Table 102. Randomized Lot ID Locations (Continued) Info Page Memory Address Address 5C FE5C 5D FE5D 5E FE5E 5F FE5F 61 FE61 62 FE62 64 FE64 65 FE65 67 FE67 68 FE68 6A FE6A 6B FE6B 6D FE6D 6E FE6E ...

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PS022825-0908 ® Z8 Encore! XP F082A Series Product Specification Flash Option Bits 168 ...

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... The Z8 Encore! XP element 128 bytes. This memory can perform over 100,000 write cycles. Operation The NVDS is implemented by special purpose Zilog memory, which are not user-accessible. These special-purpose routines use the Flash memory to store the data. The routines incorporate a dynamic addressing scheme to maximize the write/erase endurance of the Flash ...

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R0. The bit fields of this status byte are defined in The contents of the status byte are undefined for write operations to illegal addresses. Also, user code must pop the address and data bytes off ...

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Also, the user code must pop the address byte off the stack. The read routine uses 9 bytes of stack space in addition to the one byte of address pushed by the user. Sufficient memory ...

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Table 104. NVDS Read Time (Continued) Operation Read (128 byte array) Write (16 byte array) Write (64 byte array) Write (128 byte array) Illegal Read Illegal Write If NVDS read performance is critical to your software architecture, there are some ...

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On-Chip Debugger The Z8 Encore! XP (OCD) that provides advanced debugging features including: • Single pin interface. • Reading and writing of the register file. • Reading and writing of program and data memory. • Setting of breakpoints and watchpoints. ...

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Operation OCD Interface The on-chip debugger uses the DBG pin for communication with an external host. This one-pin interface is a bi-directional, open-drain interface that transmits and receives data. Data transmission is half-duplex, in that transmit and receive cannot occur ...

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RS-232 TX RS-232 RX Figure 25. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2) DEBUG Mode The operating characteristics of the devices in DEBUG mode are: • The eZ8 CPU fetch unit stops, idling the eZ8 CPU, ...

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If the PA2/RESET pin is held Low while a 32-bit key sequence is issued to the PA0/ DBG pin, the DBG feature is unlocked. After releasing PA2/RESET pulled High. At this point, the PA0/DBG pin may be ...

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The Auto-Baud Detector/Generator is clocked by the system clock. The minimum baud rate is the system clock frequency divided by 512. For optimal operation with asynchronous datastreams, the maximum recommended baud rate is the system clock frequency divided by 8. ...

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High. Because of the open-drain nature of the DBG pin, the host can send a Serial Break to the OCD even if the OCD is transmitting a character. OCD Unlock Sequence (8-Pin Devices Only) Because of pin-sharing on the 8-pin ...

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Breakpoints in Flash Memory The instruction is opcode BRK byte in Flash memory. To implement a Breakpoint, write address, overwriting the current instruction. To remove a Breakpoint, the corresponding page of Flash memory must be erased and reprogrammed with the ...

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Command Debug Command Write Register Read Register Write Program Memory Read Program Memory Write Data Memory Read Data Memory Read Program Memory CRC Reserved Step Instruction Stuff Instruction Execute Instruction Reserved 13H–FFH In the following bulleted list of OCD Commands, ...

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Write Memory, Read Memory, Write Register, Read Register, Read Memory CRC, Step Instruction, Stuff Instruction, and Execute Instruction commands. ← DBG → DBG → DBG • Write OCD Control Register (04H)—The Write OCD Control Register command writes the data that ...

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Read Register (09H)—The Read Register command reads data from the Register File. Data can be read 1–256 bytes at a time (256 bytes can be read by setting size to 0). If the device is not in DEBUG mode ...

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DBG ← DBG ← DBG • Read Data Memory (0DH)—The Read Data Memory command reads from Data Memory. This command is equivalent to the LDE and LDEI instructions. Data can be read 1 to 65536 bytes at a time ...

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If the device is not in DEBUG mode or the Flash Read Protect Option bit is enabled, this command reads and discards one byte. ← DBG ← DBG On-Chip Debugger Control Register Definitions OCD Control Register The OCD Control register ...

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DBGACK—Debug Acknowledge This bit enables the debug acknowledge feature. If this bit is set to 1, the OCD sends a Debug Acknowledge character ( 0 = Debug Acknowledge is disabled Debug Acknowledge is enabled. Reserved—Must be 0. RST—Reset ...

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PS022825-0908 ® Z8 Encore! XP F082A Series Product Specification On-Chip Debugger 186 ...

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Oscillator Control The Z8 Encore! XP user-selectable: • Internal precision trimmed RC oscillator (IPO). • On-chip oscillator using off-chip crystal or resonator. • On-chip oscillator using external RC network. • External clock drive. • On-chip low power Watchdog Timer oscillator. ...

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Table 108. Oscillator Configuration and Selection Clock Source Characteristics Internal Precision • 32.8 kHz or 5.53 MHz RC Oscillator • High accuracy • No external components required External Crystal/ • 32 kHz to 20 MHz Resonator • Very high accuracy ...

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When selecting a new clock source, the system clock oscillator failure detection circuitry and the Watchdog Timer oscillator failure circuitry must be disabled. If SOFEN and WOFEN are not disabled prior to a clock switch-over possible to generate ...

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