CY7C60223-PXC Cypress Semiconductor Corp, CY7C60223-PXC Datasheet

IC MCU 8K WIRELESS 24-DIP

CY7C60223-PXC

Manufacturer Part Number
CY7C60223-PXC
Description
IC MCU 8K WIRELESS 24-DIP
Manufacturer
Cypress Semiconductor Corp
Series
enCoRe™ II CY7C602xxr
Datasheet

Specifications of CY7C60223-PXC

Core Processor
M8C
Core Size
8-Bit
Speed
12MHz
Connectivity
SPI
Peripherals
LVD, POR, WDT
Number Of I /o
20
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
24-DIP (0.300", 7.62mm)
For Use With
770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY3216 - KIT PROGRAMMER MODULAR428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
428-1797

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C60223-PXC
Manufacturer:
TEXAS
Quantity:
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Part Number:
CY7C60223-PXC
Manufacturer:
CYP
Quantity:
9 473
1. Features
Cypress Semiconductor Corporation
Document 38-16016 Rev. *F
enCoRe™ II Low Voltage (enCoRe II LV)—enhanced
Component Reduction
Enhanced 8-bit Microcontroller
Internal Memory
Low Power Consumption
In-system Reprogrammability
General Purpose I/O Ports
2. Logic Block Diagram
Internal crystalless oscillator with support for optional exter-
nal clock or external crystal or resonator
Configurable I/O for real world interface without external com-
ponents
Harvard architecture
M8C CPU speed up to 12 MHz or sourced by an external
crystal, resonator, or clock signal
256 bytes of RAM
8 Kbytes of Flash including EEROM emulation
Typically 2.25 mA at 3 MHz
5 μA sleep
Enables easy firmware update
Up to 36 GPIO pins
2 mA source current on all GPIO pins.
Configurable 8 or 50 mA per pin current sink on designated
pins
Each GPIO port supports high impedance inputs, config-
urable pull up, open drain output, CMOS and TTL inputs, and
CMOS output
Maskable interrupts on all I/O pins
Oscillator
Internal
12 MHz
CY7C601xx only
Oscillator
Crystal
Control
Clock
Low-Voltage
Detect
POR /
M8C CPU
Watchdog
Timer
198 Champion Court
enCoRe™ II Low Voltage Microcontroller
Interrupt
Control
256 Byte
RAM
4 SPI/GPIO
Pins
SPI Serial Communication
2-channel 8-bit or 1-channel 16-bit Capture Timer Registers,
which store both Rising and Falling Edge Times
Internal Low Power Wakeup Timer during Suspend Mode
Programmable Interval Timer Interrupts
Reduced RF Emissions at 27 MHz and 96 MHz
Watchdog Timer (WDT)
Low Voltage Detection with User Selectable Threshold
Voltages
Improved Output Drivers to reduce EMI
Operating Voltage from 2.7V to 3.6V DC
Operating Temperature from 0 to 70°C
Available in 24 and 40-Pin PDIP, 24-Pin SOIC, 24-Pin QSOP
and SSOP, 28-Pin SSOP, and 48-Pin SSOP
Advanced Development Tools based on Cypress PSoC
Industry Standard Programmer Support
Master or slave operation
Configurable up to 2 Mbit per second transfers
Supports half duplex single data line mode for optical sensors
Two registers each for two input pins
Separate registers for rising and falling edge capture
Simplifies interface to RF inputs for wireless applications
Periodic wakeup with no external components
8K Byte
Flash
16 Extended
San Jose, CA 95134-1709
I/O Pins
CY7C601xx, CY7C602xx
12-bit Timer
16 GPIO
Pins
Revised September 4, 2009
Wakeup
Capture
Timer
Timers
408-943-2600
®
Tools
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Related parts for CY7C60223-PXC

CY7C60223-PXC Summary of contents

Page 1

... MHz Oscillator Clock Control Crystal Oscillator CY7C601xx only POR / Low-Voltage Detect Cypress Semiconductor Corporation Document 38-16016 Rev. *F enCoRe™ II Low Voltage Microcontroller ■ SPI Serial Communication ❐ Master or slave operation ❐ Configurable Mbit per second transfers ❐ Supports half duplex single data line mode for optical sensors ■ ...

Page 2

Applications The CY7C601xx and CY7C602xx are targeted for the following applications: ■ PC wireless HID devices ❐ Mice (optomechanical, optical, trackball) ❐ Keyboards ❐ Presenter tools ■ Gaming ❐ Joysticks ❐ Gamepad ■ General purpose wireless applications ❐ Remote ...

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... P2.1 10 P3.1 P2 P3.0 P0 P1.7 T1O1/P0 P1.6/SMISO TIO0/P0 P1.5/SMOSI INT2/P0 P1.4/SCLK INT1/P0 P1.3/SSEL INT0/P0 P1.2 23 CLKOUT/P0 CLKIN/P0.0 P1 P1.0 SS CY7C601xx, CY7C602xx CY7C60223 24-Pin QSOP P1 P0 P1.6/SMISO TIO1/P0.6 22 P1.5/SMOSI 3 21 P1.4/SCLK TIO0/P0.5 4 P3.1 20 INT2/P0 P3.0 INT1/P0 P1.3/SSEL INT0/P0 CLKOUT\P0 CLKIN\P0 P1.1 P2 P1.0 P2.0 ...

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Pin Assignments Table 6-1. Pin Assignments SSOP PDIP SSOP QSOP SOIC PDIP ...

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Table 6-1. Pin Assignments (continued SSOP PDIP SSOP QSOP SOIC PDIP ...

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Register Summary Table 7-1. enCoRe II LV Register Summary The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF. Addr Name P0DATA P0.7 P0.6/TIO1 ...

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Table 7-1. enCoRe II LV Register Summary (continued) The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF. Addr Name IOSCTR foffset[2:0] 35 XOSCTR Reserved ...

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CPU Architecture This family of microcontrollers is based on a high performance, 8-bit, Harvard architecture microprocessor. Five registers control the primary operation of the CPU core. These registers are affected by various instructions, but are not directly accessible through ...

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Accumulator Register Table 9-2. CPU Accumulator Register (CPU_A) Bit # 7 6 Field Read/Write – – Default 0 0 Bit [7:0]: CPU Accumulator [7:0] 8-bit data value holds the result of any logical or arithmetic instruction that uses a ...

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Addressing Modes 9.2.1 Source Immediate The result of an instruction using this addressing mode is placed in the A register, the F register, the SP register, or the X register, which is specified as part of the instruction opcode. ...

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Destination Indexed The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register forming the address that points to the location ...

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Source Indirect Post Increment The result of an instruction using this addressing mode is placed in the Accumulator. Operand address pointing to a location within the memory space, which contains an address (the indirect address) for ...

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Table 10-1. Instruction Set Summary Sorted Numerically by Opcode Order (continued) [1, 2] Instruction Format Flags SUB [X+expr SUB [expr], expr SUB [X+expr], expr C, Z ...

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Memory Organization 11.1 Flash Program Memory Organization Figure 11-1. Program Memory Space with Interrupt Vector Table after reset 16-bit PC Document 38-16016 Rev. *F Address 0x0000 Program execution begins here after a reset 0x0004 POR/LVD 0x0008 INT0 0x000C SPI ...

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Data Memory Organization The CY7C601xx and CY7C602xx microcontrollers provide up to 256 bytes of data RAM After Reset 8-bit PSP Top of RAM Memory 11.3 Flash This section describes the Flash block of enCoRe II LV. Much of the ...

Page 16

Two important variables used for all functions are KEY1 and KEY2. These variables help discriminate between valid and inadvertent SSCs. KEY1 always has a value of 3Ah, while KEY2 has the same value as the stack pointer when the SROM ...

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WriteBlock Function The WriteBlock function is used to store data in Flash. Data is moved 64 bytes at a time from SRAM to Flash using this function. The WriteBlock function first checks the protection bits and deter- mines if ...

Page 18

Table 11-8. ProtectBlock Parameters Name Address Description KEY1 0,F8h 3Ah KEY2 0,F9h Stack Pointer value when SSC is executed CLOCK 0,FCh Clock Divider used to set the write pulse width DELAY 0,FEh For a CPU speed of 12 MHz set ...

Page 19

SROM Table Read Description The Silicon IDs for enCoRe II LV devices are stored in SROM tables in the part, as shown in The Silicon ID can be read out from the part using SROM table reads. This is ...

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F8h Silicon ID Table 0 [15-8] Family / Table 1 Die ID Table 2 32 kHz Table 3 LPOSCTR at 3.30V Table 4 Table 5 Table 6 Table 7 11.6.1 Checksum Function The Checksum function calculates a 16-bit checksum over ...

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Clocking The enCoRe II LV has two internal oscillators, the internal 24 MHz oscillator and the 32 kHz low power oscillator. The internal 24 MHz oscillator is designed such that it is trimmed to an output frequency of 24 ...

Page 22

When using the 32 kHz oscillator, the PITMRL/H is read until two consecutive readings match before sending and receiving data. The following firmware example assumes the developer is interested in the lower byte of the PIT. Read_PIT_counter: mov A, reg[PITMRL] ...

Page 23

P0.1 CLKOUT P0.0 CLKIN CLK_EXT CLK_24MHz Table 12-2. CPU Clock Configuration (CPUCLKCR) [0x30] [R/W] Bit # 7 6 Field Read/Write – – Default 0 0 Bit [7:1]: Reserved Bit 0: CPU CLK Select 0 = Internal 24 MHz Oscillator 1 ...

Page 24

Table 12-3. OSC Control 0 (OSC_CR0) [0x1E0] [R/W] Bit # 7 6 Field Reserved Read/Write – – Default 0 0 Bit [7:6]: Reserved Bit 5: No Buzz During sleep (the Sleep bit is set in the CPU_SCR on periodically to ...

Page 25

Table 12-4. Clock I/O Configuration (CLKIOCR) [0x32] [R/W] Bit # 7 6 Reserved Field Read/Write – – Default 0 0 Bit [7:5]: Reserved Bit 4: XOSC Select This bit, when set, selects the external crystal oscillator clock as clock source ...

Page 26

Figure 12-2. Programmable Interval Timer Block Diagram Configuration System Clock Clock Timer 12.2.3 Timer Capture Clock (TCAPCLK) The Timer Capture clock (TCAPCLK) is sourced from the external crystal oscillator, the internal 24 MHz oscillator or the internal 32 kHz low ...

Page 27

Table 12-1. Timer Clock Configuration (TMRCLKCR) [0x31] [R/W] Bit # 7 6 Field TCAPCLK Divider Read/Write R/W R/W Default 1 0 Bit [7:6]: TCAPCLK Divider [1:0] TCAPCLK Divider controls the TCAPCLK divisor Divider Value ...

Page 28

Internal Clock Trim Table 12-1. IOSC Trim (IOSCTR) [0x34] [R/W] Bit # 7 6 Field foffset[2:0] Read/Write R/W R/W Default 0 0 The IOSC Calibrate Register is used to calibrate the internal oscillator. The reset value is undefined, but ...

Page 29

LPOSC Trim Table 12-3. LPOSC Trim (LPOSCTR) [0x36] [R/W] Bit # 7 6 Field 32 kHz Low Reserved Power Read/Write R/W – Default 0 – This register is used to calibrate the 32 kHz low speed oscillator. The reset ...

Page 30

Reset The microcontroller supports two types of resets: Power on Reset (POR) and Watchdog Reset (WDR). When reset is initiated, all registers are restored to their default states and all interrupts are disabled. The occurrence of a reset is ...

Page 31

Power On Reset POR occurs every time the power to the device is switched on. POR is released when the supply is typically 2.6V for the upward supply transition, with typically hysteresis during the power on ...

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Sleep Sequence The Sleep bit is an input into the sleep logic circuit. This circuit is designed to sequence the device into and out of the hardware sleep state. The hardware sequence to put the device to sleep is ...

Page 33

Wakeup Sequence When asleep, the only event that wakes the system interrupt. The global interrupt enable of the CPU flag register need not be set. Any unmasked interrupt wakes the system up optional for ...

Page 34

Low Voltage Detect Control Table 15-1. Low Voltage Control Register (LVDCR) [0x1E3] [R/W] Bit # 7 6 Field Reserved Read/Write – – Default 0 0 This register controls the configuration of the Power on Reset and Low Voltage Detection ...

Page 35

POR Compare State Table 15-2. Voltage Monitor Comparators Register (VLTCMP) [0x1E4] [R] Bit # 7 6 Field Read/Write – – Default 0 0 This read-only register allows reading the current state of the LVD and PPOR comparators. Bit [7:2]: ...

Page 36

General Purpose I/O Ports 16.1 Port Data Registers 16.1.1 P0 Data Table 16-1. P0 Data Register (P0DATA)[0x00] [R/W] Bit # 7 6 Field P0.7 P0.6/TIO1 Read/Write R/W R/W Default 0 0 This register contains the data for Port 0. ...

Page 37

P2 Data Table 16-3. P2 Data Register (P2DATA) [0x02] [R/W] Bit # 7 6 Field Read/Write R/W R/W Default 0 0 This register contains the data for Port 2. Writing to this register sets the bit values to be ...

Page 38

High Sink When set, the output sinks mA. When clear, the output sinks mA. On the CY7C601xx, only the P3.7, P2.7, P0.1, and P0.0 have 50 mA sink drive capability. Other pins have ...

Page 39

P0.1/CLKOUT Configuration Table 16-2. P0.1/CLKOUT Configuration (P01CR) [0x06] R/W] Bit # 7 6 Field CLK Output Int Enable Read/Write R/W R/W Default 0 0 This pin is shared between the P0.1 GPIO use and the CLKOUT pin for the ...

Page 40

P0.5/TIO0–P0.6/TIO1 Configuration Table 16-4. P0.5/TIO0–P0.6/TIO1 Configuration (P05CR–P06CR) [0x0A–0x0B] [R/W] Bit # 7 6 Field TIO Output Int Enable Read/Write R/W R/W Default 0 0 These registers control the operation of pins P0.5 through P0.6, respectively. P0.5 and P0.6 are ...

Page 41

P1.1 Configuration Table 16-7. P1.1 Configuration (P11CR) [0x0E] [R/W] Bit # 7 6 Field Reserved Int Enable Read/Write – R/W Default 0 0 This register controls the operation of the P1.1 pin. The pull up resistor on this pin ...

Page 42

P1.4–P1.6 Configuration (SCLK, SMOSI, SMISO) Table 16-10. P1.4–P1.6 Configuration (P14CR–P16CR) [0x11–0x13] [R/W] Bit # 7 6 Field SPI Use Int Enable Read/Write R/W R/W Default 0 0 These registers control the operation of pins P1.4–P1.6, respectively. These registers exist ...

Page 43

P3 Configuration Table 16-13. P3 Configuration (P3CR) [0x16] [R/W] Bit # 7 6 Field Reserved Int Enable Read/Write – R/W Default CY7C602xx, this register controls the operation of pins P3.0–P3.1. In CY7C601xx, this register controls the ...

Page 44

Serial Peripheral Interface (SPI) The SPI Master and Slave Interface core logic runs on the SPI clock domain. The SPI clock is a divider off of the CPUCLK when in Master Mode. SPI is a four pin serial interface ...

Page 45

SPI Data Register Table 17-1. SPI Data Register (SPIDATA) [0x3C] [R/W] Bit # 7 6 Field Read/Write R/W R/W Default 0 0 When read, this register returns the contents of the receive buffer. When written, it loads the transmit ...

Page 46

Table 17-3. SPI Mode Timing vs. LSB First, CPOL, and CPHA LSB First CPHA CPOL ...

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Table 17-4. SPI SCLK Frequency SCLK CPUCLK SCLK Frequency when Select Divisor CPUCLK = 12 MHz MHz MHz 10 48 250 kHz 11 96 125 kHz 17.3 SPI Interface Pins The SPI interface uses ...

Page 48

Table 18-2. Free Running Timer High Order Byte (FRTMRH) [0x21] [R/W] Bit # 7 6 Field Read/Write R/W R/W Default 0 0 Bit [7:0]: Free Running Timer [15:8] When reading the free running timer, the low order byte is read ...

Page 49

Table 18-2. Capture Interrupt Enable (TCAPINTE) [0x2B] [R/W] Bit # 7 6 Field Reserved Read/Write – – Default 0 0 Bit [7:4]: Reserved Bit 3: Cap1 Fall Enable 0 = Disable the capture 1 falling edge interrupt 1 = Enable ...

Page 50

Table 18-6. Timer Capture 1 Falling (TCAP1F) [0x25] [R/W] Bit # 7 6 Field Read/Write R R Default 0 0 Bit [7:0]: Capture 1 Falling [7:0] This register holds the value of the free running timer when the last falling ...

Page 51

Table 18-2. Programmable Interval Timer High (PITMRH) [0x27] [R] Bit # 7 6 Field Reserved Read/Write -- -- Default 0 0 Bit [7:4]: Reserved Bit [3:0]: Prog Internal Timer [11:8] This register holds the high order nibble of the 12-bit ...

Page 52

Figure 18-3. Timer Functional Sequence Diagram Document 38-16016 Rev. *F CY7C601xx, CY7C602xx Page [+] Feedback ...

Page 53

Figure 18-4. 16-Bit Free Running Counter Loading Timing Diagram clk_sys write valid addr write data FRT reload ready Clk Timer 12b Prog Timer 12b reload interrupt Capture timer clk 16b free running counter load 16b free 00A0 00A1 00A2 00A3 ...

Page 54

Interrupt Controller The interrupt controller and its associated registers allow the user’s code to respond to an interrupt from almost every functional block in the enCoRe II LV devices. The registers associated with the interrupt controller are disabled either ...

Page 55

Architectural Description An interrupt is posted when its interrupt conditions occur. This results in the flip-flop in Figure 19-1 clocking in a ‘1’. The interrupt remains posted until the interrupt is taken or until it is cleared by writing ...

Page 56

Interrupt Registers 19.4.1 Interrupt Clear Register The Interrupt Clear Registers (INT_CLRx) are used to enable the individual interrupt sources’ ability to clear posted interrupts. When an INT_CLRx register is read, any bits that are set indicates an interrupt has ...

Page 57

Interrupt Mask Registers The Interrupt Mask Registers (INT_MSKx) enable the individual interrupt sources’ ability to create pending interrupts. There are four Interrupt Mask Registers INT_MSK1, INT_MSK2, and INT_MSK3) which are referred to in general as INT_MSKx. If cleared, each ...

Page 58

Table 19-6. Interrupt Mask 1 (INT_MSK1) [0xE1] [R/W] Bit # 7 6 Field TCAP0 Prog Interval Int Enable Timer Int Enable Read/Write R/W R/W Default 0 0 Bit 7: TCAP0 Interrupt Enable 0 = Mask TCAP0 interrupt 1 = Unmask ...

Page 59

Absolute Maximum Ratings Storage Temperature ..................................... –40°C to +90°C Ambient Temperature with Power Applied....... –0°C to +70°C Supply Voltage on V Relative to V ............–0.5V to +7. Input Voltage ................................. –0. Voltage ...

Page 60

AC Characteristics Parameter Description Clock T External Clock Duty Cycle ECLKDC T External Clock Frequency ECLK2 F Internal Main Oscillator Frequency IMO F Internal Low Power Oscillator ILO GPIO Timing T Output Rise Time R_GPIO T Output Fall Time ...

Page 61

GPIO Pin Output Voltage 10% SS SCK (CPOL=0) T SCKH SCK (CPOL=1) T MDO MOSI MISO MSB T MSU Document 38-16016 Rev. *F Figure 20-2. GPIO Timing Diagram T T R_GPIO Figure 20-3. SPI Master Timing, CPHA = 1 ...

Page 62

SS T SSS SCK (CPOL=0) T SCKH SCK (CPOL=1) MOSI T T SDO MISO SS SCK (CPOL=0) T SCKH SCK (CPOL=1) T MDO1 MOSI MSB MSB MISO T T MSU MHD Document 38-16016 Rev. *F Figure 20-4. SPI Slave Timing, ...

Page 63

... Ordering Information Ordering Code CY7C60123-PVXC CY7C60123-PXC CY7C60113-PVXC CY7C60223-PXC CY7C60223-SXC CY7C60223-QXC 22. Package Handling Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory. A label on the packaging has details about actual bake temperature and the minimum bake time to remove this moisture. ...

Page 64

Package Diagrams 0.597[15.163] 0.615[15.621] 0.004[0.101] 0.0118[0.299] 0.050[1.270] 0.013[0.330] TYP. 0.019[0.482] Document 38-16016 Rev. *F Figure 23-1. 24-Pin (300-Mil) SOIC S13 NOTE : 1. JEDEC STD REF MO-119 PIN BODY LENGTH DIMENSION DOES ...

Page 65

REF. 12 0.150 0.157 0.228 0.244 13 SEATING PLANE 0.053 0.069 0.004 0.004 0.010 Figure 23-4. 28-Pin (5.3 mm) Shrunk Small Outline Package O28 Document 38-16016 Rev. *F Figure 23-3. 24-Pin QSOP O241 PIN 0.337 ...

Page 66

Figure 23-6. 48-Pin Shrunk Small Outline Package O48 Document 38-16016 Rev. *F Figure 23-5. 40-Pin (600-Mil) Molded DIP P17 CY7C601xx, CY7C602xx 51-85019-*A 51-85061-*C Page [+] Feedback ...

Page 67

Document History Page Document Title: CY7C601xx, CY7C602xx enCoRe™ II Low Voltage Microcontroller Document Number: 38-16016 Orig. of Submission Rev. ECN Change ** 327601 BON See ECN *A 400134 BHA See ECN *B 505222 TYJ See ECN *C 524104 KKVTMP ...

Page 68

... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document 38-16016 Rev. *F PSoC is a registered trademark and enCoRe is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. psoc.cypress.com clocks ...

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