W78E051B40DL Nuvoton Technology Corporation of America, W78E051B40DL Datasheet

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W78E051B40DL

Manufacturer Part Number
W78E051B40DL
Description
IC MCU 8-BIT 4K FLASH 40-DIP
Manufacturer
Nuvoton Technology Corporation of America
Series
W78r
Datasheet

Specifications of W78E051B40DL

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

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Part Number:
W78E051B40DL
Quantity:
8 000
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
8.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES ................................................................................................................................. 3
PIN CONFIGURATIONS ............................................................................................................ 4
PIN DESCRIPTION..................................................................................................................... 5
BLOCK DIAGRAM ...................................................................................................................... 6
FUNCTIONAL DESCRIPTION ................................................................................................... 7
6.1
6.2
6.3
6.4
6.5
6.6
6.7
SECURITY BITS ....................................................................................................................... 12
7.1
7.2
7.3
ELECREICAL CHARACTERISTICS......................................................................................... 14
8.1
8.2
8.3
New Defined Peripheral.................................................................................................. 7
Reduce EMI Emission .................................................................................................... 8
Watchdog Timer ............................................................................................................. 9
Clock ............................................................................................................................. 10
Power Management...................................................................................................... 10
Reset............................................................................................................................. 11
On-Chip ROM Characteristics ...................................................................................... 11
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
6.7.7
Lock Bit ......................................................................................................................... 13
MOVC Inhibit................................................................................................................. 13
Encryption ..................................................................................................................... 13
Absolute Maximum Ratings .......................................................................................... 14
D.C. Characteristics...................................................................................................... 14
A.C. Characteristics ...................................................................................................... 15
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
Read Operation ..............................................................................................................11
Output Disable Condition................................................................................................11
Program Operation .........................................................................................................11
Program Verify Operation ...............................................................................................11
Erase Operation .............................................................................................................11
Erase Verify Operation ...................................................................................................11
Program/Erase Inhibit Operation ....................................................................................12
Clock Input Waveform ....................................................................................................16
Program Fetch Cycle......................................................................................................16
Data Read Cycle ............................................................................................................16
Data Write Cycle.............................................................................................................17
Port Access Cycle ..........................................................................................................17
Program Operation .........................................................................................................17
8-BIT MICROCONTROLLER
- 1 -
W78E51B Data Sheet
Publication Release Date: Sep. 6, 2005
Revision A7

Related parts for W78E051B40DL

W78E051B40DL Summary of contents

Page 1

Table of Contents- 1. GENERAL DESCRIPTION ......................................................................................................... 3 2. FEATURES ................................................................................................................................. 3 3. PIN CONFIGURATIONS ............................................................................................................ 4 4. PIN DESCRIPTION..................................................................................................................... 5 5. BLOCK DIAGRAM ...................................................................................................................... 6 6. FUNCTIONAL DESCRIPTION ................................................................................................... 7 6.1 New Defined Peripheral.................................................................................................. 7 6.2 Reduce EMI Emission ...

Page 2

TIMING WAVEFORMS ............................................................................................................. 18 9.1 Program Fetch Cycle .................................................................................................... 18 9.2 Data Read Cycle........................................................................................................... 18 9.3 Data Write Cycle........................................................................................................... 19 9.4 Port Access Cycle......................................................................................................... 19 9.5 Program Operation ....................................................................................................... 20 10. TYPICAL APPLICATION CIRCUITS ........................................................................................ 21 10.1 Expanded External ...

Page 3

... Built-in power management Code protection mechanism Packages: − DIP 40: W78E51B-40 − PLCC 44: W78E51BP-40 − PQFP 44: W78E51BF-40 − Lead Free (RoHS) DIP 40: − Lead Free (RoHS) PLCC 44: W78E051B40PL − Lead Free (RoHS) PQFP 44: W78E051B40FL W78E051B40DL Publication Release Date: Sep. 6, 2005 - 3 - W78E51B Revision A7 ...

Page 4

PIN CONFIGURATIONS 40-Pin DIP (W78E51B) 44-Pin PLCC (W78E51BP ...

Page 5

PIN DESCRIPTION SYMBOL EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external ROM. It should be kept high to access internal ROM. The ROM address and EA data will not be presented on the bus ...

Page 6

BLOCK DIAGRAM P1.0 ~ Port Port 1 1 P1.7 Latch INT2 Interrupt INT3 Timer 0 Timer 1 UART P3.0 Port Port P3.7 Latch Port 4 P4.0 Latch Port ~ 4 P4.3 XTAL1 B ACC T2 T1 ...

Page 7

FUNCTIONAL DESCRIPTION The W78E51B architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 128 bytes of RAM, two timer/counters, and a serial port. The processor supports 111 different opcodes and references both a ...

Page 8

Port 4 Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are alternative ...

Page 9

Watchdog Timer The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event timer basically a set of dividers that divide the ...

Page 10

WIDL IDLE OSC 1/12 Watchdog Timer Block Diagram Typical Watch-dog time-out period when OSC = 20 MHz PS2 PS1 PS0 ...

Page 11

Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to ...

Page 12

Program/Erase Inhibit Operation This operation allows parallel erasing or programming of multiple chips with different data. When P3. P3. except for the P3.6 and P3.7 pins, the individual chips ...

Page 13

Reserved Lock bit, logic 0 : active B1 : MOVC inhibit, logic 0 : the MOVC instruction in external memory cannot access the code in internal memory. logic 1 ...

Page 14

ELECREICAL CHARACTERISTICS 8.1 Absolute Maximum Ratings PARAMETER DC Power Supply Input Voltage Operating Temperature Storage Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 8.2 D.C. ...

Page 15

DC Characteristics, continued PARAMETER Input Low Voltage (Except RST) Input Low Voltage (*4) RST Input Low Voltage (*4) XTAL1 Input High Voltage (Except RST) Sink Current P1, P2, P3, P4 Input High Voltage (*4) RST Input High Voltage (*4) XTAL1 ...

Page 16

Clock Input Waveform XTAL1 PARAMETER Operating Speed Clock Period Clock High Clock Low Notes: 1. The clock may be stopped indefinitely in either state. 2. The T specification is used as a reference in other specifications There ...

Page 17

Data Write Cycle PARAMETER ALE Low to WR Low Data Valid to WR Low Data Hold from WR High WR Pulse Width Note: " Δ " (due to buffer driving delay and wire loading nS. 8.3.5 Port ...

Page 18

TIMING WAVEFORMS 9.1 Program Fetch Cycle S1 XTAL1 ALE PSEN PORT 2 T AAH PORT 0 Code 9.2 Data Read Cycle S4 S5 XTAL1 ALE PSEN PORT 2 A0-A7 PORT ...

Page 19

Timing Waveforms, continued 9.3 Data Write Cycle S4 S5 XTAL1 ALE PSEN PORT 2 PORT 0 A0-A7 WR 9.4 Port Access Cycle XTAL1 ALE T PDS PORT INPUT SAMPLE A8-A15 DATA OUT T T ...

Page 20

Timing Waveforms, continued 9.5 Program Operation V P2 (A15... A0 P3 (CE P3.3 IH (OECTRL P3 (OE (A7... A0) V ...

Page 21

TYPICAL APPLICATION CIRCUITS 10.1 Expanded External Program Memory and Crystal XTAL1 XTAL2 CRYSTAL 8 RST C1 C2 INT0 12 13 INT1 ...

Page 22

Typical Application Circuits, continued 10.2 Expanded External Data Memory and Oscillator OSCILLATOR 8 W78E51B AD0 3 39 ...

Page 23

PACKAGE DIMENSIONS 11.1 40-pin DIP 11.2 44-pin PLCC θ Seating Plane ...

Page 24

Package Dimensions, continued 11.3 44-pin PQFP See Detail F Seating Plane θ Detail F - ...

Page 25

REVISION HISTORY VERSION DATE A4 July, 2001 A5 June, 2004 A6 April 20, 2005 A7 Sep. 6, 2005 Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, ...

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