ST7FMC1K2TCE STMicroelectronics, ST7FMC1K2TCE Datasheet
ST7FMC1K2TCE
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ST7FMC1K2TCE Summary of contents
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MCU with nested interrupts, Flash, 10-bit ADC, brushless motor control, five timers, SPI, LINSCI™ Features Memories ■ – 60K dual voltage Flash Program memo ROM with read-out protection capability, In-application programming and In-circuit pro- gramming. ...
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PWM AUTO-RELOAD TIMER (ART ...
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RESET VALUE OF UNAVAILABLE PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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INTRODUCTION The ST7MCx device is member of the ST7 micro- controller family designed for mid-range applica- tions with a Motor Control dedicated peripheral. All devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion ...
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ST7MC1xx/ST7MC2xx 2 PIN DESCRIPTION Figure 2. 80-Pin LQFP 14x14 Package Pinout 1 (HS) MCO3 (HS) MCO4 2 (HS) MCO5 3 MCES 4 PG0 5 PG1 6 PG2 7 PG3 8 OSC1 9 OSC2 10 VSS_1 11 VDD_1 12 PWM3 / ...
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PIN DESCRIPTION (Cont’d) Figure 3. 64-Pin LQFP 14x14 Package Pinout (HS) MCO3 (HS) MCO4 (HS) MCO5 MCES OSC1 OSC2 PWM3 / PA0 PWM2 / (HS) PA1 PWM1 / PA2 AIN0 / PWM0 / PA3 ARTCLK ...
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ST7MC1xx/ST7MC2xx PIN DESCRIPTION (Cont’d) Figure 4. 32-Pin SDIP Package Pinouts AIN0 / PWM0 / PA3 AIN1 / ARTIC1 / PA5 MCVREF / PB0 (HS) 20mA high sink capability eix associated external interrupt vector * Once the MTC peripheral is ON, ...
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PIN DESCRIPTION (Cont’d) Figure 5. 56-Pin SDIP Package Pinouts OCMP1_B / PE1 PWM2 / (HS) PA1 AIN0 / PWM0 / PA3 ARTCLK / (HS) PA4 AIN1 / ARTIC1 / PA5 AIN3 / MOSI / PB5 AIN4 / SS /(HS) PB7 ...
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ST7MC1xx/ST7MC2xx PIN DESCRIPTION (Cont’d) Figure 6. 44-Pin LQFP Package Pinouts (HS) MCO3 (HS) MCO4 (HS) MCO5 MCES OSC1 OSC2 AIN0 / PWM0 / PA3 AIN1 / ARTIC1 / PA5 MCVREF / PB0 (HS) 20mA high sink ...
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PIN DESCRIPTION (Cont’d) Figure 7. 32-Pin LQFP 7x7 Package Pinout (HS) MCO3 (HS) MCO4 (HS) MCO5 AIN0 / PWM0 / PA3 AIN1 / ARTIC1 / PA5 (HS) 20mA high sink capability eix associated external interrupt vector * Once the MTC ...
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ST7MC1xx/ST7MC2xx PIN DESCRIPTION (Cont’d) For external pin connection guidelines, See “ELECTRICAL CHARACTERISTICS” on page 247. Legend / Abbreviations for Type input output supply Input level Dedicated analog input In/Output level ...
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Table 1. ST7MC Device Pin Description Pin n° Pin Name PB0/MCVREF I PB1/MCIA PB2/MCIB PB3/MCIC ...
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ST7MC1xx/ST7MC2xx Table 1. ST7MC Device Pin Description Pin n° Pin Name PF0 MCDEM AIN8 PF1/MCZEM AIN9 PF2/MCO AIN10 ...
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Table 1. ST7MC Device Pin Description Pin n° Pin Name PH6 PH7 PE0 OCMP2_B PE1 OCMP1_B ...
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ST7MC1xx/ST7MC2xx to an alternate function. PC4 is no longer usable as a digital I/O.l 10. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The ...
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REGISTER & MEMORY MAP As shown in Figure 8, the MCU is capable of ad- dressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations 2Kbytes of RAM ...
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ST7MC1xx/ST7MC2xx Table 2. Hardware Register Map Address Block 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h PBDR 0004h Port B PBDDR 0005h PBOR 0006h PCDR 0007h Port C PCDDR 0008h PCOR 0009h PDDR 000Ah Port D PDDDR 000Bh PDOR ...
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Table 2. Hardware Register Map Address Block 0024h ITSPR0 0025h ITSPR1 0026h ITC ITSPR2 0027h ITSPR3 0028h EICR 0029h FLASH FSCR WDGCR 002Ah WATCHDOG 002Bh WDGWR 002Ch MCCSR MCC 002Dh MCCBCR 002Eh ADCCSR 002Fh ADC ADCDRMSB 0030h ADCDRLSB 0031h TACR2 ...
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ST7MC1xx/ST7MC2xx Table 2. Hardware Register Map Address Block 0050h MTIM 0051h MTIML 0052h MZPRV 0053h MZREG 0054h MCOMP 0055h MDREG 0056h MWGHT 0057h MPRSR 0058h MIMR 0059h MISR 005Ah MCRA 005Bh MCRB 005Ch MCRC MTC 005Dh MPHST (page 0) 005Eh ...
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Table 2. Hardware Register Map Address Block 0074h PWMDCR3 0075h PWMDCR2 0076h PWMDCR1 0077h PWMDCR0 0078h PWMCR 0079h PWM ART ARTCSR 007Ah ARTCAR 007Bh ARTARR 007Ch ARTICCSR 007Dh ARTICR1 007Eh ARTICR2 007Fh OPAMP OACSR Legend: x=undefined, R/W=read/write Notes: 1. The ...
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ST7MC1xx/ST7MC2xx 4 FLASH PROGRAM MEMORY 4.1 INTRODUCTION The ST7 dual voltage High Density Flash (HDFlash non-volatile memory that can be electrically erased as a single block or by individu- al sectors and programmed on a Byte-by-Byte ba- sis ...
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FLASH PROGRAM MEMORY (Cont’d) 4.4 ICC INTERFACE ICC (In-Circuit Communication) needs a minimum of four and up to six pins to be connected to the programming tool (see Figure – RESET: device reset – device power supply ground ...
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... Flash memory programming can be fully custom- ized (number of bytes to program, program loca- tions, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the spe- cific microcontroller device, the user needs only to implement the ICP hardware interface on the ap- ...
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CENTRAL PROCESSING UNIT 5.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 MAIN FEATURES Enable executing 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ 17 main ...
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ST7MC1xx/ST7MC2xx CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt masks and four flags representative of the result of the instruction just ...
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CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 FFh SP7 SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next free ...
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ST7MC1xx/ST7MC2xx 6 SUPPLY, RESET AND CLOCK MANAGEMENT The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. An overview ...
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OSCILLATOR The main clock of the ST7 can be generated by a crystal or ceramic resonator oscillator or an exter- nal source. The associated hardware configurations are shown in Table 4. Refer to the electrical character- istics section for ...
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ST7MC1xx/ST7MC2xx 6.2 RESET SEQUENCE MANAGER (RSM) 6.2.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET ■ Note: A reset ...
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RESET SEQUENCE MANAGER (Cont’d) The RESET pin is an asynchronous signal which plays a major role in EMS performance noisy environment recommended to follow the guidelines mentioned in the electrical characteris- tics section. 6.2.3 External Power-On ...
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ST7MC1xx/ST7MC2xx 6.3 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low Voltage Detector (LVD), Auxiliary Voltage Detector (AVD) and Clock Security System (CSS) functions managed by the SICSR register. Note: A reset can also be ...
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SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.3.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between reference value and the V IT+(AVD) ply. The V reference value for falling voltage is IT- ...
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ST7MC1xx/ST7MC2xx SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.3.3 Clock Security System (CSS) The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the in- tegration of the security features in the applica- tions based on a ...
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SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.3.5 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, page 0) Read/Write Reset Value: 000x 000x (00h) 7 AVD PAG AVD LVD Bit 7 = PAGE SICSR Register Page Selection This ...
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ST7MC1xx/ST7MC2xx SYSTEM INTEGRITY MANAGEMENT (Cont’d) SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR, page 1) Reset Value: 00000000 (00h) 7 VCO LO PLL Bit 7 = PAGE SICSR Register Page Selection This bit selects the SICSR ...
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MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK AND BEEPER (MCC/RTC) The Main Clock Controller consists of three differ- ent functions: a programmable CPU clock prescaler ■ a clock-out signal to supply external devices ■ ■ a real-time clock timer with ...
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ST7MC1xx/ST7MC2xx MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK (Cont’d) 6.4.5 Low Power Modes Mode Description No effect on MCC/RTC peripheral. Wait MCC/RTC interrupt cause the device to exit from Wait mode. No effect on MCC/RTC counter (OIE bit is Active- set), ...
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MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK (Cont’d) Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main oscillator has reached the selected ...
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ST7MC1xx/ST7MC2xx 7 INTERRUPTS 7.1 INTRODUCTION The ST7 enhanced interrupt management pro- vides the following features: Hardware interrupts ■ Software interrupt (TRAP) ■ Nested or concurrent interrupt management ■ with flexible interrupt management: – software programmable nesting levels ...
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INTERRUPTS (Cont’d) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: – the highest software priority interrupt is serviced, – if ...
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ST7MC1xx/ST7MC2xx INTERRUPTS (Cont’d) 7.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the Wait low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the Halt modes (see ...
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INTERRUPTS (Cont’d) 7.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read/Write Reset Value: 111x 1010 (xAh Bit I1, I0 Software Interrupt Priority These two bits indicate the current interrupt soft- ...
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ST7MC1xx/ST7MC2xx INTERRUPTS (Cont’d) Table 7. Dedicated Interrupt Instruction Set Instruction New Description HALT Entering Halt mode IRET Interrupt routine return JRM Jump if I1:0=11 (level 3) JRNM Jump if I1:0<>11 POP CC Pop CC from the Stack RIM Enable interrupt ...
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INTERRUPTS (Cont’d) 7.6 EXTERNAL INTERRUPTS The pending interrupts are cleared writing a differ- ent value in the ISx[1:0], IPA or IPB bits of the EICR. Note: External interrupts are masked when an I/O (configured as input interrupt) of the same ...
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ST7MC1xx/ST7MC2xx INTERRUPTS (Cont’d) Figure 24. External Interrupt Control bits PORT D [6:4] INTERRUPTS PDOR.6 PDDDR.6 PD6 IPA BIT PORT D [3:1] INTERRUPTS PDOR.3 PDDDR.3 PD3 PORT A3, PORT A[7:5] INTERRUPTS PAOR.7 PADDR.7 PA7 PORT C [3:1] INTERRUPTS PCOR.3 PCDDR.3 PC3 ...
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INTERRUPTS (Cont’d) 7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read/Write Reset Value: 0000 0000 (00h) 7 IS11 IS10 IPB IS21 IS20 Bit 7:6 = IS1[1:0] ei2 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external ...
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ST7MC1xx/ST7MC2xx EXTERNAL INTERRUPT CONTROL REGISTER (EICR) (Cont’d) - ei0 (port D6..4) External Interrupt Sensitivity IS31 IS30 IPA bit =0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and ...
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INTERRUPTS (Cont’d) Table 9. Nested Interrupts Register Map and Reset Values Address Register (Hex.) Label 0024h I1_3 ISPR0 Reset Value 0025h I1_7 ISPR1 Reset Value 0026h I1_11 ISPR2 Reset Value 0027h I1_15 ISPR3 Reset Value EICR IS11 0028h Reset Value ...
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ST7MC1xx/ST7MC2xx 8 POWER SAVING MODES 8.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 25): Slow, Wait (Slow-wait), Active- ...
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POWER SAVING MODES (Cont’d) 8.3 WAIT MODE Wait mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During Wait ...
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ST7MC1xx/ST7MC2xx POWER SAVING MODES (Cont’d) 8.4 ACTIVE-HALT AND HALT MODES Active-halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active-halt ...
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POWER SAVING MODES (Cont’d) 8.4.2 HALT MODE The Halt mode is the lowest power consumption mode of the MCU entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is ...
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ST7MC1xx/ST7MC2xx 9 I/O PORTS 9.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ripherals. An ...
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I/O PORTS (Cont’d) Figure 32. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS ALTERNATE ENABLE DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT SOURCE ( Table 10. I/O Port Mode ...
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ST7MC1xx/ST7MC2xx I/O PORTS (Cont’d) Table 11. I/O Port Configurations NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS PAD Notes: 1. When the ...
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I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ...
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ST7MC1xx/ST7MC2xx I/O PORTS (Cont’d) 9.5.1 I/O Port Implementation The I/O port register configurations are summa- rised as follows. Standard Ports PA4, PA2:0, PB5:0, PC7:4, PD7:6, PE5:0, PF5:0, PG7:0, PH7:0 MODE floating input pull-up input open drain output push-pull output Table ...
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I/O PORTS (Cont’d) Table 13. I/O Port Register Map and Reset Values Address Register (Hex.) Label Reset Value of all I/O port registers 0000h PADR 0001h PADDR MSB 0002h PAOR 0003h PBDR 0004h PBDDR MSB 0005h PBOR 0006h PCDR 0007h ...
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ST7MC1xx/ST7MC2xx 10 ON-CHIP PERIPHERALS 10.1 WINDOW WATCHDOG (WWDG) 10.1.1 Introduction The Window Watchdog is used to detect the oc- currence of a software fault, usually generated by external interference or by unforeseen logical con- ditions, which causes the application program ...
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WINDOW WATCHDOG (Cont’d) The application program must write in the WDGCR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. The ...
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ST7MC1xx/ST7MC2xx WINDOW WATCHDOG (Cont’d) 10.1.5 How to Program the Watchdog Timeout Figure 35 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Coun- ter (CNT) and the resulting timeout duration in mil- liseconds. This can ...
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WINDOW WATCHDOG (Cont’d) Figure 36. Exact Timeout Duration (t WHERE (LSB + 128 min0 t = 16384 x t max0 OSC2 t = 125ns MHz OSC2 OSC2 CNT = Value ...
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ST7MC1xx/ST7MC2xx WINDOW WATCHDOG (Cont’d) Figure 37. Window Watchdog Timing Diagram T[5:0] CNT downcounter WDGWR 3Fh T6 bit Reset 10.1.6 Low Power Modes Mode Description Slow No effect on Watchdog: The downcounter continues to decrement at normal speed. Wait No effect ...
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WINDOW WATCHDOG (Cont’d) 10.1.9 Interrupts None. 10.1.10 Register Description CONTROL REGISTER (WDGCR) Read/Write Reset Value: 0111 1111 (7Fh) 7 WDGA Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware ...
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ST7MC1xx/ST7MC2xx Table 14. Watchdog Timer Register Map and Reset Values Address Register (Hex.) Label WDGCR WDGA 002Ah Reset Value WDGWR 002Bh Reset Value 66/309 ...
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PWM AUTO-RELOAD TIMER (ART) 10.2.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto reload counter with compare/capture capabilities and of a 7-bit prescaler clock source. These resources allow five possible operating modes: – ...
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ST7MC1xx/ST7MC2xx ON-CHIP PERIPHERALS (Cont’d) 10.2.2 Functional Description Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every ris- ing edge of the clock signal possible to read or write ...
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ON-CHIP PERIPHERALS (Cont’d) Independent PWM signal generation This mode allows up to four Pulse Width Modulat- ed signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during Halt mode. Each PWMx ...
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ST7MC1xx/ST7MC2xx ON-CHIP PERIPHERALS (Cont’d) Output compare and Time base interrupt On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generat the overflow interrupt enable bit, OIE, in the ARTCSR register, ...
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ON-CHIP PERIPHERALS (Cont’d) Input capture function This mode allows the measurement of external signal pulse widths through ARTICRx registers. Each input capture can generate an interrupt inde- pendently on a selected input signal transition. This event is flagged by a ...
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ST7MC1xx/ST7MC2xx ON-CHIP PERIPHERALS (Cont’d) 10.2.3 Register Description CONTROL / STATUS REGISTER (ARTCSR) Read/Write Reset Value: 0000 0000 (00h) 7 EXCL CC2 CC1 CC0 TCE Bit 7 = EXCL External Clock This bit is set and cleared by software. It selects ...
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ON-CHIP PERIPHERALS (Cont’d) PWM CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h) 7 OE3 OE2 OE1 OE0 OP3 Bit 7:4 = OE[3:0] PWM Output Enable These bits are set and cleared by software. They enable or disable the PWM ...
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ST7MC1xx/ST7MC2xx ON-CHIP PERIPHERALS (Cont’d) INPUT CAPTURE CONTROL / STATUS REGISTER (ARTICCSR) Read/Write Reset Value: 0000 0000 (00h CS2 CS1 CIE2 Bit 7:6 = Reserved, always read as 0. Bit 5:4 = CS[2:1] Capture Sensitivity These bits are ...
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PWM AUTO-RELOAD TIMER (Cont’d) Table 15. PWM Auto-Reload Timer Register Map and Reset Values Address Register Label (Hex.) PWMDCR3 DC7 0074h Reset Value PWMDCR2 DC7 0075h Reset Value PWMDCR1 DC7 0076h Reset Value PWMDCR0 DC7 0077h Reset Value PWMCR OE3 ...
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ST7MC1xx/ST7MC2xx 10.3 16-BIT TIMER 10.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input sig- nals (input ...
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TIMER (Cont’d) Figure 44. Timer Block Diagram f CPU 8 high EXEDG 1/2 1/4 1/8 ALTERNATE EXTCLK pin CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 (Control/Status Register) ICIE OCIE TOIE FOLV2 (See note) TIMER INTERRUPT INTERNAL BUS 16-BIT ...
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ST7MC1xx/ST7MC2xx 16-BIT TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Read At t0 +Δt LS Byte Sequence completed The user must read ...
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TIMER (Cont’d) Figure 45. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 46. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER ...
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ST7MC1xx/ST7MC2xx 16-BIT TIMER (Cont’d) 10.3.3.3 Input Capture In this section, the index, i, may because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used ...
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TIMER (Cont’d) Figure 48. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 49. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: ...
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ST7MC1xx/ST7MC2xx 16-BIT TIMER (Cont’d) 10.3.3.4 Output Compare In this section, the index, i, may because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or ...
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TIMER (Cont’d) Notes: 1. After a processor write cycle to the OCiHR reg- ister, the output compare function is inhibited until the OCiLR register is also written the OCiE bit is not set, the OCMPi pin is ...
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ST7MC1xx/ST7MC2xx 16-BIT TIMER (Cont’d) Figure 51. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi=1) Figure 52. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER ...
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TIMER (Cont’d) 10.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input ...
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ST7MC1xx/ST7MC2xx 16-BIT TIMER (Cont’d) Figure 53. One Pulse Mode Timing Example IC1R 01F8 COUNTER ICAP1 OCMP1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 54. Pulse Width Modulation Mode Timing Example COUNTER 34E2 compare2 Note: 86/309 01F8 FFFC FFFD FFFE OLVL2 OLVL2 ...
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TIMER 10.3.3.6 Pulse Width Modulation Mode Note: Procedure ST7MC1xx/ST7MC2xx Pulse Width Modulation cycle Notes: ...
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ST7MC1xx/ST7MC2xx 16-BIT TIMER 10.3.4 Low Power Modes No effect on 16-bit Timer. Wait Timer interrupts cause the Device to exit from Wait mode. 16-bit Timer registers are frozen. In Halt mode, the counter stops counting until Halt mode is exited. ...
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Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. Read/Write Reset Value: ...
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Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin ...
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Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 TIMD Bit input capture (reset value input capture has occurred on the ...
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Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). 7 MSB Read Only Reset Value: Undefined This is an 8-bit ...
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Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register ...
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Timer A: 32 Timer B: 42 Reset Value Timer A: 31 OC1E Timer B: 41 Reset Value Timer A: 33 ICF1 Timer B: 43 Reset Value Timer A: 34 MSB Timer B: 44 Reset Value Timer A: 35 MSB ...
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The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. ...
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Shift Register SOD bit 96/309 1 (cont’d) Data/Address Bus Read Read Buffer Write MASTER CONTROL SERIAL CLOCK GENERATOR Interrupt request 7 SPIF WCOL OVR MODF 0 SOD SPI STATE CONTROL 7 MSTR SPIE SPE SPR2 CPOL CPHA 0 SSM ...
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A basic example of interconnections between a single master and a single slave is illustrated in Figure 56. The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master ...
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As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR regis- ter (see Figure ...
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In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). The idle state of SCK must correspond to the polarity ...
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Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 59). The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL = ...
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SERIAL PERIPHERAL INTERFACE (cont’d) 10.4.5 Error Flags 10.4.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master de- vice’s SS pin is pulled low. When a Master mode fault occurs: – The MODF bit is set and an ...
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ST7MC1xx/ST7MC2xx SERIAL PERIPHERAL INTERFACE (cont’d) 10.4.5.4 Single Master Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured using a device as the master ...
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SERIAL PERIPHERAL INTERFACE (cont’d) 10.4.6 Low Power Modes Mode Description No effect on SPI. Wait SPI interrupt events cause the device to exit from Wait mode. SPI registers are frozen. In Halt mode, the SPI is inactive. SPI opera- tion ...
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ST7MC1xx/ST7MC2xx 10.4.8 Register Description SPI CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL CPHA SPR1 Bit 7 = SPIE This bit is set and cleared by software. 0: Interrupt is inhibited 1: An ...
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SERIAL PERIPHERAL INTERFACE (cont’d) SPI CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF WCOL OVR MODF - Bit 7 = SPIF This bit is set by hardware when a transfer has been completed. ...
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ST7MC1xx/ST7MC2xx SERIAL PERIPHERAL INTERFACE (Cont’d) Table 19. SPI Register Map and Reset Values Address Register (Hex.) Label SPIDR MSB 0021h Reset Value SPICR SPIE 0022h Reset Value SPICSR SPIF 0023h Reset Value 106/309 ...
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LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) 10.5.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers a very ...
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ST7MC1xx/ST7MC2xx LINSCI™ SERIAL COMMUNICATION INTERFACE (cont’d) 10.5.4 General Description The interface is externally connected to another device by two pins: – TDO: Transmit Data Output. When the transmit- ter is disabled, the output pin returns to its I/O port configuration. ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) Figure 62. SCI Block Diagram (in Conventional Baud Rate Generator Mode) Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL SCICR2 TIE TCIE RIE SCI INTERRUPT CONTROL TRANSMITTER CLOCK f CPU ...
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ST7MC1xx/ST7MC2xx LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 10.5.5 SCI Mode - Functional Description Conventional Baud Rate Generator Mode The block diagram of the Serial Control Interface in conventional baud rate generator mode is shown in Figure 62. It uses ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 10.5.5.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the ...
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ST7MC1xx/ST7MC2xx LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 10.5.5.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 10.5.5.4 Conventional Baud Rate Generation The baud rates for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: f CPU (16 PR ...
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ST7MC1xx/ST7MC2xx LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) Figure 64. SCI Baud Rate and Extended Prescaler Block Diagram EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED TRANSMITTER PRESCALER REGISTER EXTENDED RECEIVER PRESCALER REGISTER EXTENDED PRESCALER RECEIVER RATE CONTROL f CPU /16 /PR ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 10.5.5.6 Receiver Muting and Wake-up Feature In multiprocessor configurations it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead ...
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ST7MC1xx/ST7MC2xx LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 10.5.6 Low Power Modes Mode Description No effect on SCI. Wait SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. Halt In Halt mode, the SCI stops ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) 10.5.8 SCI Mode Register Description STATUS REGISTER (SCISR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE OR Bit 7 = TDRE This bit is set by hardware when the ...
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ST7MC1xx/ST7MC2xx LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) CONTROL REGISTER 1 (SCICR1) Read/Write Reset Value: x000 0000 (x0h SCID M WAKE PCE 1) This bit has a different function in LIN mode, please refer to the LIN ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) CONTROL REGISTER 2 (SCICR2) Read/Write Reset Value: 0000 0000 (00h) 7 TIE TCIE RIE ILIE TE 1) This bit has a different function in LIN mode, please refer to the LIN mode register ...
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ST7MC1xx/ST7MC2xx LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) BAUD RATE REGISTER (SCIBRR) Read/Write Reset Value: 0000 0000 (00h) 7 SCP1 SCP0 SCT2 SCT1 SCT0 Note: When LIN slave mode is disabled, the SCI- BRR register controls the conventional baud rate ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) Read/Write Reset Value: 0000 0000 (00h) 7 ERPR ERPR ERPR ERPR ERPR Bits 7:0 = ERPR[7:0] 8-bit Extended Receive Prescaler Register The ...
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ST7MC1xx/ST7MC2xx LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) 10.5.9 LIN Mode - Functional Description. The block diagram of the Serial Control Interface, in LIN slave mode is shown in It uses six registers: – 3 control registers: SCICR1, SCICR2 and SCICR3 ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) Figure 65. LIN Characters 8-bit Word length (M bit is reset) Data Character Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit Idle Line LIN Synch Field Start Bit0 Bit1 Bit2 Bit3 ...
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ST7MC1xx/ST7MC2xx LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) Figure 66. SCI Block Diagram in LIN Slave Mode Transmit Data Register (TDR) TDO RDI SCICR2 TIE TCIE INTERRUPT CONTROL f CPU LIN SLAVE BAUD RATE AUTO SYNCHRONIZATION SCIBRR LPR7 f CPU ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 10.5.9.3 LIN Reception In LIN mode the reception of a byte is the same as in SCI mode but the LINSCI has features for han- dling the LIN Header automatically (identifier de- tection) ...
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ST7MC1xx/ST7MC2xx LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 10.5.9.4 LIN Error Detection LIN Header Error Flag The LIN Header Error Flag indicates that an invalid LIN Header has been detected. When a LIN Header Error occurs: – The LHE flag ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) If LHE bit is set due to this error during Fields other than LIN Synch Field or if LASE bit is reset then the current received Header is discarded and the SCI searches ...
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ST7MC1xx/ST7MC2xx LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 10.5.9.5 LIN Baud Rate Baud rate programming is done by writing a value in the LPR prescaler or performing an automatic resynchronization as described below. Automatic Resynchronization To automatically adjust the baud ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) Figure 69. LDIV Read / Write Operations When LDUM = 0 Write LPFR Write LPR MANT(7:0) MANT(7:0) Read LPR Figure 70. LDIV Read / Write Operations When LDUM = 1 Write LPFR Write ...
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ST7MC1xx/ST7MC2xx LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 10.5.9.7 LINSCI Clock Tolerance LINSCI Clock Tolerance when unsynchronized When LIN slaves are unsynchronized (meaning no characters have been transmitted for a relatively long time), the maximum tolerated deviation of the LINSCI ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 10.5.9.9 Error due to LIN Synch measurement The LIN Synch Field is measured over eight bit times. This measurement is performed using a counter clocked by the CPU clock. The edge detections are ...
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ST7MC1xx/ST7MC2xx LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) 10.5.10 LIN Mode Register Description STATUS REGISTER (SCISR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE LHE Bits 7:4 = Same function as in SCI mode, please refer ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) CONTROL REGISTER 2 (SCICR2) Read/Write Reset Value: 0000 0000 (00h) 7 TIE TCIE RIE ILIE TE Bits 7:2 Same function as in SCI mode, please re- fer to Section 10.5.8 SCI Mode Register ...
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ST7MC1xx/ST7MC2xx LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) SCICR2 register is set, the LHDM bit selects the Wake-Up method (replacing the WAKE bit). 0: LIN Synch Break Detection Method 1: LIN Identifier Field Detection Method Bit 2 = LHIE LIN ...
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) LIN PRESCALER FRACTION REGISTER (LPFR) Read/Write Reset Value: 0000 0000 (00h) 7 LPFR Bits 7:4 = Reserved. Bits 3:0 = LPFR[3:0] Fraction of LDIV These 4 bits define ...
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ST7MC1xx/ST7MC2xx LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d) LIN HEADER LENGTH REGISTER (LHLR) Read Only Reset Value: 0000 0000 (00h). 7 LHL7 LHL6 LHL5 LHL4 LHL3 Note: In LIN Slave mode when LASE = 1 or LHDM = 1, the ...
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SERIAL COMMUNICATION INTERFACE (Cont’d) Table 21. SCI Register Map and Reset Values Addr. Register Name (Hex.) SCI1SR 0018h Reset Value SCI1DR 0019h Reset Value SCI1BRR 001Ah LPR (LIN Slave Mode) Reset Value SCI1CR1 001Bh Reset Value SCI1CR2 001Ch Reset Value ...
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ST7MC1xx/ST7MC2xx 10.6 MOTOR CONTROLLER (MTC) 10.6.1 Introduction The ST7 Motor Controller (MTC) can be seen as a Three-Phase Pulse Width Modulator multiplexed on six output channels and a Back Electromotive Force (BEMF) zero-crossing detector for sensor- less control of Permanent ...
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MOTOR CONTROLLER (Cont’d) Table 23. MTC Registers Register Description MTIM Timer Counter Register Timer LSB (mode depend- MTIML ent) MZPRV Capture Z Register n-1 MZREG Capture Z Register n MCOMP Compare C Register n+1 MDREG Demagnetization Reg. MWGHT A Weight ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) 10.6.3 Application Example: PM BLDC motor drive This example shows a six-step command se- quence for a 3-phase permanent magnet DC brushless motor (PM BLDC motor). shows the phase steps and voltage, while 24 shows the ...
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MOTOR CONTROLLER (Cont’d) Figure 73. Chronogram of Events (in Autoswitched Mode processing Cn processing Wait for C Wait for C Wait for D Wait ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) Figure 74. Example of Command Sequence for 6-step Mode (typical 3-phase PM BLDC Motor Control) Σ Σ Step 1 2 Switch Node ...
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MOTOR CONTROLLER (Cont’d) All detections of Z events are done during a short n measurement window while the high side switch is turned off. For this reason the PWM signal is ap- plied on the high side switches. When the ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) Finally, the PWM modulated voltage generated by the power stage is smoothed by the motor induct- ance to get sinusoidal currents in the stator wind- ings. The induction motor being asynchronous, there is no need to ...
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MOTOR CONTROLLER (Cont’d) Figure 76. Typical command signals of a three-phase induction motor Phase A * Phase B * Phase C * PWM period PWM output Duty Cycle 51% 50% 49% PWM output Duty Cycle * These simplified chronograms represent ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) 10.6.5 Functional Description The MTC can be split into five main parts as shown in the simplified block diagram in Each of these parts may be configured for different purposes: INPUT DETECTION BLOCK with a comparator, ...
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MOTOR CONTROLLER (Cont’d) Figure 77. Simplified MTC Block Diagram DELAY MANAGER or SPEED MEASURE UNIT (not represented) DELAY WEIGHT DELAY = WEIGHT x Zn MEASUREMENT WINDOW GENERATOR (I) PWM MANAGER 12-bit counter Phase U Phase V Phase W [Z] : ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) Figure 78. Input Stage in Sensorless or Sensor Mode Input Block MCIA A MCIB B MCIC C MCVREF Sampling frequency 12-bit PWM generator Signal U Notes: Updated/Shifted on R Reg Updated with Reg on C n+1 ...
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MOTOR CONTROLLER (Cont’d) 10.6.6.2 Sensorless Mode This mode is used to detect BEMF zero crossing and end of demagnetization events. The analog phase multiplexer connects the non- excited motor winding to an analog 100mV hyster- esis comparator referred to a ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) 10.6.6.3 D Event detection In sensorless mode, the D Window Filter becomes active after each C event. It blanks out the D event during the time window defined by the DWF[3:0] bits in the MDFR register ...
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MOTOR CONTROLLER (Cont’d) 10.6.6.4 Z Event Detection In sensorless mode, the Z window filter becomes active after each D event. It blanks out the Z event during the time window defined by the ZWF[3:0] bits in the MZFR register (see ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) Table 30 shows the event control selected by the ZVD and CPB bits. In most cases, the D and Z events have opposite edge polarity, so the ZVD bit is usually 0. Table 30. ZVD and ...
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MOTOR CONTROLLER (Cont’d) 10.6.6.5 Demagnetization (D) Event At the end of the demagnetization phase, current no longer goes through the free-wheeling diodes. The voltage on the non-excited winding terminal goes from one of the power rail voltages to the common ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) Table 31. Demagnetisation (D) Event Generation (example for ZVD=0) HDM Meaning bit Simulated Mode 0 (SDM bit =1 and HDM bit = 0) Hardware/Simulat- ed Mode 1 (SDM bit = 1 and HDM bit = 1) ...
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MOTOR CONTROLLER (Cont’d) 10.6.6.6 Z Event Generation (BEMF Zero Crossing) When both C and D events have occurred, the PWM may be switched to another group of outputs (depending on the OS[2:0] bits in the MCRB regis- ter) and the ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) Figure 82. Z Event Generation MCRB Register MPOL Register CPB bit* n MPOL Register REO bit D S Sample detection SPLG bit DS[3:0] bits ...
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MOTOR CONTROLLER (Cont’d) 10.6.6.7 Protection for Z event detection H To avoid an erroneous detection of a hardware zero-crossing event, a filter can be enabled by set- ting the PZ bit in the MCRA register. This filter will ensure the ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) 10.6.6.8 Position Sensor Mode In position sensor mode (SR=1 in MCRA register), the rotor position information is given to the periph- eral by means of logical data on the three inputs MCIA, MCIB and MCIC (Hall ...
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MOTOR CONTROLLER (Cont’d) 10.6.6.9 Sampling block For a full digital solution, the phase comparator output sampling frequency is the frequency of the PWM signal applied to the switches and the sam- pling for the Z event detection in sensorless mode ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) Depending on the frequency and the duty cycle of the PWM signal, the delay inserted before sam- pling could cause it sample the signal OFF time in- stead of the ON time. In this case an ...
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MOTOR CONTROLLER (Cont’d) In conclusion, there are 4 sampling types that are available for Z event detection in sensorless mode. 1. Sampling at the end of the OFF time of the PWM signal at the PWM frequency 2. Sampling, at ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) 10.6.6.10 Commutation Noise Filter For D event detection and for Z event detection (when SPLG bit is set while DS[3:0] bits are reset), sampling is done at f during the PWM ON or SCF OFF time ...
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MOTOR CONTROLLER (Cont’d) Figure 87. Functional Diagram of Z Detection after D Event Switch Sampling Clock[D] -> Sampling Clock[ Begin Z Window Filter turned on ZWF[3:0] bits in MZFR register No Side change on Output ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) 10.6.6.11 Speed Sensor Mode This mode is entered whenever the Tacho Edge Selection bits in the MPAR register are not both re- set (TES[1: 11). The corresponding block diagram is shown in ...
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MOTOR CONTROLLER (Cont’d) 10.6.6.13 Encoder Mode (IS[1:0] = 11) Figure 90 shows the signals delivered by a stand- ard digital incremental encoder and associated in- formation: – Two 90° phased square signals with variable frequency proportional to the speed; they ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) Note If only one encoder output is available, it may be input either on MCIA or MCIB and an encoder clock signal will still be generated (in this case the frequency will be 50% less than ...
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MOTOR CONTROLLER (Cont’d) Note on using the 3 MCIx pins as standard I/Os: When none of the MCIx pins are needed in the application (for instance when driving an in- duction motor in open loop), they can be used as ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) 10.6.7 Delay Manager Figure 91. Overview of MTIM Timer in Switched and Autoswitched Mode Z H § MZREG [ Compare H S MCRC register SZ bit § MZPRV [Z ] n-1 ...
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MOTOR CONTROLLER (Cont’d) the MCOMP and MTIM register is enabled before a write access in the MCOMP register. This means that if the SC bit is set and no write access is done after in the MCOMP register ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) Figure 92. Step Ratio Functional Diagram MPRSR Register MTIM Timer control over T MTIM Timer Overflow Begin Ratio < Fh? Yes Ratio = Ratio + 1 MZREG = MZREG / 2 MZPRV = MZPRV/2 MDREG = ...
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MOTOR CONTROLLER (Cont’d) 10.6.7.2 Autoswitched Mode In this mode, using the hardware commutation event C (SC bit reset in MCRC register), the H MCOMP register content is automatically comput real-time as described below and in 93. The C ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) generation. Otherwise, the C event will never oc- cur. Note 4: When simulated commutation mode is en- abled, the built-in check is active the value written in the MCOMP register is less than or ...
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MOTOR CONTROLLER (Cont’d) Figure 94. Output on pins MCDEM and MCZEM with debug option (DG bit=1) MCDEM MCZEM C D Debug outputs in Sensorless mode MCDEM MCZEM C Debug outputs in Sensor mode MCDEM C C MCZEM U events Debug ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) Note on using the auto-updated MTIM timer: The auto-updated MTIM timer works accurately within its operating range but some care has to be taken when processing timer-dependent data such as the step duration for regulation or ...
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MOTOR CONTROLLER (Cont’d) 10.6.7.4 Built-in Checks and Controls for simulated events As described in Figure 91. on page MDREG and MCOMP registers are capture/com- pare registers. The Compare registers are write accessible and can be used to generate simulated events. ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) When using hardware commutation C quence of events needed events and the value written in the registers are checked at different times. If SDM bit is set, meaning simulated demagnetisa- tion, a value ...
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MOTOR CONTROLLER (Cont’d) Figure 96. Simulated commutation event generation with only 1 Hall effect sensor (SC bit =1) After C interrupt MCOMP is written for C if MCOMP<=MTIM Immediate C generation interrupt SC ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) The Figure 98 gives the step ratio register value (left axis) and the number of BEMF sampling dur- ing one electrical step with the corresponding ac- curacy on the measure (right axis function of ...
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MOTOR CONTROLLER (Cont’d) Table 40. Step Frequency/Period Range (4MHz) Step Ratio Bits ST[3:0] in MPRSR Step Frequency Register 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 41. Modes of Accessing MTIM ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) 10.6.7.5 Speed Measurement Mode Motor speed can be measured using two methods depending on sensor type: period measurement or pulse counting. Typical sensor handling is de- scribed here. Incremental encoders allows accurate speed measurement by providing ...
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MOTOR CONTROLLER (Cont’d) Hall sensors (or equivalent sensors providing posi- tion information) are widely used for motor control. There are two cases to be considered: – BLDC motor or six-step synchronous motor drive; “Sensor Mode” is recommended in this case, ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) Figure 102. Overview of MTIM Timer in Speed Measurement Mode Registers: MSCR* MPHST* MPAR* Bits: ECM Tacho Capture MTIM Read access RTC interrupt MTIM C MZREG Notes: § = Register updated on R event * = ...
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MOTOR CONTROLLER (Cont’d) A logic block manages capture operations de- pending on the sensor type. A capture is initiated on an active edge (“Tacho capture” event) when using a tachogenerator encoder is used, the capture is triggered on ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) Three kinds of interrupt can be generated in Speed Sensor Mode, as summarized in 104: – C interrupt, when a capture event occurs; this in- terrupt shares resources (Mask bit and Flag) with the Commutation event ...
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MOTOR CONTROLLER (Cont’d) 10.6.7.6 Summary The use of the Delay manager registers for the various available modes is summarized in 42. Table 42. MTIM Timer-related Registers Name Reset Value MTIM 00h MTIML 00h MZREG 00h MZPRV 00h MCOMP 00h MDREG ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) 10.6.8.2 Over Current Handling in Voltage mode When the current limitation interrupt is enabled by setting the CLIM bit in the MIMR register (available only in Voltage mode), the OCV bit in MCRB reg- ister will ...
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MOTOR CONTROLLER (Cont’d) Table 44. Current Window filter Setting CFW2 CFW1 CFW0 Blanking window length Blanking window off ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) 10.6.8.5 Current feedback amplifier In both current and voltage mode, the current feedback from the motor can be amplified before entering the comparator. This is done by an inte- grated Op-amp that can be used when ...
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MOTOR CONTROLLER (Cont’d) This sets the minimum off time of the PWM signal generated by this internal clock. This off time can vary depending on the output of the current feed- back comparator. In sensor mode (SR=1) and when the ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) 10.6.9 Channel Manager The channel manager consists of: – A Phase State register with preload and polarity function Figure 108. Channel Manager Block Diagram PWM Generator Sampling frequency Current comparator output MCFR Register CFF[2:0] bits MCRA ...
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MOTOR CONTROLLER (Cont’d) 10.6.9.1 MPHST Phase State Register A preload register enables software to asynchro- nously update the channel configuration for the next step (during the previous commutation inter- rupt routine for example): the OO[5:0] bits in the MPHST register ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) Figure 109. PWM application in Voltage or Current sensorless mode (see OS2 PWM behaviour after C and before D 0 High Channels 1 Low Channels OS2 Demagnetization High 000 1 Low 0 High ...
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MOTOR CONTROLLER (Cont’d) Figure 110. PWM application in Voltage or Current Sensor Mode (see OS2 PWM behaviour after C - and before Z 0 High Channels 1 Low Channels High 0x0 Low 1 0 High 0x1 ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) 10.6.9.3 Dead Time Generator When using typical triple half bridge topology for power converters, precautions must be taken to avoid short circuits in half bridges. This is ensured by driving high and low side switches with ...
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MOTOR CONTROLLER (Cont’d) Figure 113. Dead Time waveform with delay greater than the positive PWM pulse Input Output A Output B Table 52. Dead time programming and example T Deadtime expression DTG5 DTG4 dtg 0 X 2xT (DTG[4..0]+ ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) Figure 114. Channel Manager Output Block Diagram with PWM generator delivering 3 PWM signals MREF Register HFE[1:0] bits HFRQ[2:0] bits MPOL Register OP[5:0] bits OCV bit 1 MRCA Register CLIM bit MOE bit 1 CLI bit ...
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MOTOR CONTROLLER (Cont’d) If the PCN bit is reset, one of the three PWM sig- nals (the one set by the compare U register pair) or the output of the measurement window generator (depending on if the driving mode is ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) Figure 115. Channel Manager Output Block Diagram with PWM generator delivering 1 PWM signal PWM generator U channel Sampling frequency Current comparator output MPAR Register OE[5:0] bits MREF Register HFE[1:0] bits HFRQ[2:0] bits MPOL Register OP[5:0] ...
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MOTOR CONTROLLER (Cont’d) 10.6.9.4 Programmable Chopper Depending on the application hardware (use of a pulse transformer, for example), a chopper may be needed for the PWM signal. The MREF register al- lows the chopping frequency and mode to be pro- ...
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ST7MC1xx/ST7MC2xx MOTOR CONTROLLER (Cont’d) 10.6.10 PWM Generator Block The PWM generator block produces three inde- pendent PWM signals based on a single carrier frequency with individually adjustable duty cycles. Depending on the motor driving method, one or three of these ...