UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet
UPSD3234A-40U6T
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UPSD3234A-40U6T Summary of contents
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... UPSD3233B-40U6 40 UPSD3233BV-24U6 24 UPSD3234A-40T6 40 UPSD3234A-40U6 40 UPSD3234BV-24U6 24 January 2009 UPSD3234A, UPSD3234BV UPSD3233B, UPSD3233BV Flash programmable system devices with 8032 MCU and 64 Kbit SRAM LQFP52 (T) 52-lead, thin, quad flat package ■ A/D converter – Four channels, 8-bit resolution, 10 µs ■ Communication interfaces – USB v1.1, low-speed 1.5 Mbps, 3 endpoints – ...
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... Arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.11 Logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.12 Data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.12.1 2.12.2 2.12.3 2.13 Boolean instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 B register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Program status word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Registers R0~ Data pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Direct addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Indirect addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Register-specific addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Immediate constants addressing ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 2.14 Relative offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.15 Jump instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.16 Machine cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3 UPSD323xx hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 MCU module description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1 Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.1 External Int0 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.2 Timer 0 and 1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.3 Timer 2 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interrupt ...
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... I C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 15.1 Serial status register (SxSTA: S1STA, S2STA 15.2 Data shift register (SxDAT: S1DAT, S2DAT 4/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Mode Mode Mode Mode Baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Using Timer 1 to generate baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Using Timer/counter 2 to generate baud rates . . . . . . . . . . . . . . . . . . . 68 More about Mode More about Mode 1 ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 15.3 Address register (SxADR: S1ADR, S2ADR DDC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 16.1 Special Function register for the DDC interface . . . . . . . . . . . . . . . . . . . . 89 16.1.1 16.1.2 16.2 Host type detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 16.3 DDC1 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 16.4 DDC2B protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 17 USB hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 17.1 USB related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 17.2 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 17 ...
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... Output macrocell (OMC 130 23.5 Product term allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 23.5.1 6/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Read memory sector protection status . . . . . . . . . . . . . . . . . . . . . . . . 115 Reading the Erase/Program status bits . . . . . . . . . . . . . . . . . . . . . . . . 115 Data polling flag (DQ7 116 Toggle flag (DQ6 116 Error flag (DQ5) ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 23.5.2 23.5.3 23.6 Input macrocells (IMC 133 24 I/O ports (PSD module 134 24.1 General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 24.2 Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 24.3 MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 24.4 PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 24.5 Address Out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 24 ...
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... Absolute maximum ratings (electrical sensitivity 160 31.3.1 31.3.2 31.3 and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 33 Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 34 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 35 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 8/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 FTB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Software recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Prequalification trials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Electro-static discharge (ESD 160 Latch- 160 Dynamic latch- 160 ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 1 UPSD323xx description The UPSD323xx Series combines a fast 8051-based microcontroller with a flexible memory structure, programmable logic, and a rich peripheral mix including USB, to form an ideal embedded controller. At its core is an industry-standard 8032 MCU operating up to 40MHz. A JTAG serial interface is used for In-System Programming (ISP little as 10 seconds, perfect for manufacturing and lab development ...
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... UPSD323xx description Figure 1. UPSD323xx block diagram P3.0:7 P1.0:7 P4.0:7 USB+, USB– 10/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV uPSD323x (3) 16-bit Timer/ 8032 Counters MCU (2) Core Programmable External Decode and Interrupts Page Logic UART0 (8) GPIO, Port 3 General Purpose Programmable (8) GPIO, Port 1 Logic, 16 Macrocells ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 2. TQFP52 connections PD1/CLKIN JTAG TDO JTAG TDI USB– (1) PC4/TERR_ PC3/TSTAT PC2/V STBY JTAG TCK JTAG TMS 1. Pull-up resistor required on pin 5 (2 kΩ for 3 V devices, 7.5 kΩ for 5 V devices) for all 52-pin devices, with or without USB function ...
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... NC = Not Connected Table 2. 80-pin package pin description Port Signal pin name AD0 AD1 AD2 AD3 AD4 AD5 AD6 12/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Pin In/ no. out Basic External Bus: Multiplexed 36 I/O Address/Data bus A1/D1 37 I/O Multiplexed Address/Data bus A0/D0 38 I/O Multiplexed Address/Data bus A2/D2 ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 2. 80-pin package pin description (continued) Port Signal pin name AD7 P1.0 T2 P1.1 TX2 P1.2 RxD1 P1.3 TxD1 P1.4 ADC0 P1.5 ADC1 P1.6 ADC2 P1.7 ADC3 A8 A9 A10 A11 P3.0 RxD0 P3.1 TxD0 P3.2 EXINT0 P3.3 EXINT1 P3 ...
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... PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 14/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Pin In/ no. out Basic 18 I/O General I/O port pin Pull-up resistor required (2 kΩ for 8 I devices, 7.5 kΩ for 5 V devices ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 2. 80-pin package pin description (continued) Port Signal pin name JTAG TMS JTAG TCK PC3 TSTAT PC4 TERR_ JTAG TDI JTAG TDO PC7 PD1 CLKIN PD2 Vcc Vcc GND GND GND USB 1.1 52-pin package I/O port ...
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... Registers The 8032 has several registers; these are the Program Counter (PC), Accumulator (A), B Register (B), the Stack Pointer (SP), the Program Status Word (PSW), General purpose registers (R0 to R7), and DPTR (Data Pointer register). 16/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV MAIN FLASH INT. RAM SFR ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 5. 8032 MCU registers 2.2.1 Accumulator The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional tests. The Accumulator can be used as a 16-bit register with B Register as shown below. Figure 6. Configuration of BA 16-bit registers 2 ...
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... PSD module. Figure 8. PSW (Program Status Word) register Auxillary Carry Flag General Purpose Flag 18/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV MSB RS1 RS0 OV PSW Carry Flag Register Bank Select Flags ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 2.3 Program memory The program memory consists of two Flash memories: the main Flash memory ( Mbit) and the Secondary Flash memory (256 Kbit). The Flash memory can be mapped to any address space as defined by the user in the PSDsoft Tool. It can also be mapped to Data memory space during Flash memory update or programming ...
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... The bit-addressable SFRs are those whose address ends in 0h and 8h. The bit addresses in this area are 80h to FFh. Table 3. RAM address Byte address (in hexadecimal) ¯ FFh 30h MSB 2Fh 7F 2Eh 77 2Dh 6F 2Ch 67 2Bh 5F 2Ah 57 29h 4F 28h 47 27h 3F 26h 37 25h 2F 24h 27 23h 1F 20/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Bit address (hex ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 3. RAM address (continued) Byte address (in hexadecimal) ¯ 22h 17 21h 0F 20h 07 1Fh 18h 17h 10h 0Fh 08h 07h 00h 2.9 Addressing modes The addressing modes in UPSD323xx devices instruction set are as follows 1. Direct addressing 2. Indirect addressing 3. Register addressing 4 ...
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... DPTR or PC) points to the base of the table, and the Accumulator is set up with the table entry number. The address of the table entry in Program memory is formed by adding the Accumulator data to the base pointer. 22/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Program Memory 55h 40h ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Example: movc A, @A+DPTR Figure 12. Indexed addressing 2.10 Arithmetic instructions The arithmetic instructions is listed in that can be used with each instruction to access the <byte> operand. For example, the ADD A, <byte> instruction can be written as: ADD a, 7FH (direct addressing) ADD A, @R0 (indirect addressing) ...
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... MSB rolls into the LSB position. For a right rotation, the LSB rolls into the MSB position. The SWAP A instruction interchanges the high and low nibbles within the Accumulator. This is a useful operation in BCD manipulations. For example, if the Accumulator contains a 24/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Operation Dir <byte> = <byte> ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV binary number which is known to be less than 100, it can be quickly converted to BCD by the following code: MOVE B,#10 DIV AB SWAP A ADD A,B Dividing the number by 10 leaves the tens digit in the low nibble of the Accumulator, and the ones digit in the B register. The SWAP and ADD instructions move the tens digit to the high nibble of the Accumulator, and the ones digit to the low nibble ...
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... The loop executed from LOOP to CJNE for R1 = 2EH, 2DH, 2CH, and 2BH. At that point the digit that was originally shifted out on the right has propagated to location 2AH. Since that location should be left with 0s, the lost digit is moved to the Accumulator. 26/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Operation A = <src> <dest> <dest> = <src> ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 7. Shifting a BCD number 2 digits to the right (using direct MOVs: 14 bytes) MOV A,2Eh MOV 2Eh,2Dh MOV 2Dh,2Ch MOV 2Ch,2Bh MOV 2Bh,#0 Table 8. Shifting a BCD number 2 digits to the right (using direct XCHs: 9 bytes) CLR A XCH A,2Bh XCH A,2Ch ...
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... Table 11. Lookup table READ instruction Mnemonic MOVC A,@A+DPTR MOVC A,@A+PC 28/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Mnemonic MOVX A,@Ri MOVX @Ri,A MOVX A,@DPTR MOVX @DPTR,a READ program memory at (A+DPTR) READ program memory at (A+PC) Table 11 Operation READ external RAM @Ri ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 2.13 Boolean instructions The UPSD323xx devices contain a complete Boolean (single-bit) processor. One page of the internal RAM contains 128 address-able bits, and the SFR space can support up to 128 addressable bits as well. All of the port lines are bit-addressable, and each one can be treated as a separate single-bit port ...
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... The instruction is 2 bytes long, consisting of the opcode and the relative offset byte. The jump distance is limited to a range of -128 to +127 bytes relative to the instruction following the SJMP. 30/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Operation .AND. bit .AND. .NOT. bit .OR. bit ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV The LJMP instruction encodes the destination address as a 16-bit constant. The instruction is 3 bytes long, consisting of the opcode and two address bytes. The destination address can be anywhere in the 64K Program Memory space. The AJMP instruction encodes the destination address as an 11-bit constant. The instruction is 2 bytes long, consisting of the opcode, which itself contains 3 of the 11 address bits, followed by another byte containing the low 8 bits of the destination address ...
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... If the first is less than the second, then the Carry Bit is set (1). If the first is greater than or equal to the second, then the Carry Bit is cleared. 32/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Operation Jump to addr Jump to A+DPTR ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 2.16 Machine cycles A machine cycle consists of a sequence of six states, numbered S1 through S6. Each state time lasts for two oscillator periods. Thus, a machine cycle takes 12 oscillator periods or 1µs if the oscillator frequency is 12MHz. Refer to devices. Each state is divided into a Phase 1 half and a Phase 2 half. State Sequence in UPSD323xx devices shows that retrieve/execute sequences in states and phases for various kinds of instructions ...
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... Architecture overview Figure 13. State sequence in UPSD323xx devices Osc. (XTAL2) a. 1-Byte, 1-Cycle Instruction, e.g. INC A b. 2-Byte, 1-Cycle Instruction, e.g. ADD A, adrs c. 1-Byte, 2-Cycle Instruction, e.g. INC DPTR d. 1-Byte, 2-Cycle MOVX Instruction 34/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Read next Read next opcode and ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 3 UPSD323xx hardware description The UPSD323xx devices have a modular architecture with two main functional modules: the MCU module and the PSD module. The MCU module consists of a standard 8032 core, peripherals and other system supporting functions. The PSD module provides configurable Program and Data memories to the 8032 CPU core ...
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... T2CON T2MOD ( ( ( PSCL0L ( ( PWMCON 98 SCON SBUF ( P1SFS 36/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV UCON0 UCON1 UCON2 S1DAT S1ADR S2CON RAMBUF DDCDAT DDCADR DDCCON RCAP2L RCAP2H TL2 PSCL0H PSCL1L PSCL1H PWM4P PWM4W PWM0 PWM1 PWM2 SCON2 SBUF2 P3SFS P4SFS USTA UADR UDR0 UDT1 ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 15. SFR memory map (continued) (1) 88 TCON TMOD ( Register can be bit addressing Table 16. List of all SFRs Reg Name DPL 83 DPH 87 PCON SMOD SMOD1 88 TCON TF1 TR1 89 TMOD Gate C/T 8A TL0 8B TL1 8C TH0 8D TH1 P1SFS P1S7 P1S6 93 P3SFS ...
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... PWM3 A6 WDRST EDDC A7 IEA PWM4P AB PWM4W AE WDKEY PSCL0L B2 PSCL0H B3 PSCL1L B4 PSCL1H PDDC B7 IPA T2CON TF2 EXF2 38/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Bit Register Name PWME CFG4 CFG3 ES2 - ET2 ES ET1 PS2 PT2 PS PT1 RCLK TCLK EXEN2 CFG2 CFG1 CFG0 EUSB EX1 ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 16. List of all SFRs (continued) Reg Name 7 C9 T2MOD CA RCAP2L CB RCAP2H CC TL2 CD TH2 D0 PSW CY AC S1SETU S2SETUP D4 RAMBUF D5 DDCDAT D6 DDCADR D7 DDCCON — EX_DAT D8 S1CON CR2 ENI1 D9 S1STA GC Stop DA S1DAT DB S1ADR DC S2CON CR2 EN1 DD S2STA GC Stop DE S2DAT DF S2ADR ...
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... Configures Port pin between CMOS, Open Drain or Slew rate. Bit 08 Drive (Port A) Input Macrocell 0A (Port A) Enable Out Reads the status of the output enable control to the Port pin 0C (Port A) 40/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Bit Register Name UDT1.5 UDT1.4 UDT1.3 UDT0.5 UDT0.4 UDT0 ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 17. PSD module register address offset (continued) CSIOP addr Register name 7 offset 01 Data In (Port B) 03 Control (Port B) Data Out (Port 05 B) Direction (Port Drive (Port B) Input Macrocell 0B (Port B) Enable Out 0D (Port B) 10 Data In (Port C) Data Out (Port ...
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... B4 PMMR2 * E0 Page Periph mode 1. (Register address = CSIOP address + address offset; where CSIOP address is defined by user in PSDsoft) * indicates bit is not used and must be set to ‘0’. 42/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Bit register name Sec6_ Sec5_ Sec4_ Sec3_ Sec2_ Prot Prot ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 5 Interrupt system There are interrupt requests from 10 sources as follows. ● INT0 external interrupt ● 2nd USART interrupt ● Timer 0 interrupt 2 ● interrupt ● INT1 external interrupt (or ADC interrupt) ● DDC interrupt ● Timer 1 interrupt ● USB interrupt ● ...
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... The interrupt service routine will have to check the various USART registers to determine the source and clear the corresponding flag. ● Both USART’s are identical, except for the additional interrupt controls in the Bit 4 of the additional interrupt control registers (A7h, B7h) 44/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 15. Interrupt system Table 18. SFR register description SFR Reg Add Name IEA EDDC — — B7 IPA PDDC — — — 5.9 Interrupt priority structure Each interrupt source can be assigned one of two priority levels. Interrupt priority levels are defined by the interrupt priority special function register IP and IPA ...
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... ET2 ET1 2 EX1 1 ET0 0 EX0 46/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Int0 I²C Int1 DDC USB Disable all interrupts interrupt with be acknowledged 1: each interrupt source is individually enabled or disabled by setting or clearing its enable bit Reserved Enable Timer 2 Interrupt Enable USART Interrupt Enable Timer 1 Interrupt ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 21. Description of the IEA bits Bit Symbol 7 EDDC 6 — 5 — 4 ES2 3 — 2 — 1 EI2C 0 EUSB Table 22. Description of the IP bits Bit Symbol 7 — 6 — 5 PT2 PT1 2 PX1 1 PT0 0 PX0 Table 23. Description of the IPA bits Bit Symbol 7 PDDC 6 — ...
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... Table 24. Vector addresses Source 2nd USART Timer 0 Timer 1 1st USART Timer 2+EXF2 48/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Int0 I²C Int1 DDC USB Vector address 0003h 004Bh 000Bh 0043h ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 6 Power-saving mode Two software selectable modes of reduced power consumption are implemented. 6.1 Idle mode In Idle mode, the following functions are switched Off. ● CPU (Halted) The following functions remain Active during Idle mode: ● External Interrupts ● ...
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... Once in Power-down mode, the oscillator is stopped. The contents of the on-chip RAM and the Special Function Register are preserved. The Power-down mode can be terminated by an external RESET. 50/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Double baud data rate bit UART Double baud data rate bit 2nd UART LVR disable bit (active High) ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 7 I/O ports (MCU module) The MCU module has five ports: Port 0, Port 1, Port 2, Port 3, and Port 4. (Refer to the PSD module section on I/O ports A,B,C and D). Ports P0 and P2 are dedicated for the external address and data bus and is not available in the 52-pin package devices. ...
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... Port type and description Figure 16. Port type and description (Part 1) Symbol RESET WR, RD,ALE, PSEN XTAL1, XTAL2 PORT0 52/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 0=Port 4.5 0=Port 4.4 0=Port 4.3 1=PWM 2 1=PWM 1 1=PWM Circuit Out I ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 17. Port type and description (Part 2) Symbol PORT1 <3:0>, PORT3, PORT4<7:3,1:0> PORT2 PORT1 < 7:4 > PORT4.2 USB - , USB + In/ Circuit Out I/O I/O I/O I/O + – I/O ports (MCU module) Function Bidirectional I/O port with internal pull-ups Schmitt input ...
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... Both are operated in parallel resonance. XTAL1 is the high gain amplifier input, and XTAL2 is the output. To drive the UPSD323xx devices externally, XTAL1 is driven from an external source and XTAL2 left open-circuit. Figure 18. Oscillator 54/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV XTAL1 XTAL2 XTAL1 MHz ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 9 Supervisory There are four ways to invoke a reset and initialize the UPSD323xx devices. 1. Via the external RESET pin 2. Via the internal LVR block 3. Via USB bus reset signaling 4. Via Watchdog Timer (WDT) The RESET mechanism is illustrated in Each RESET source will cause an internal reset signal active. The CPU responds by executing an internal reset and puts the internal registers in a defined state ...
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... The USB reset is generated by a detection on the USB bus RESET signal. A single-end zero on its upstream port for times will set RSTF Bit in UISTA register. If Bit 6 (RSTE) of the UIEN Register is set, the detection will also generate the RESET signal to reset the CPU and other peripherals in the MCU. 56/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 10 Watchdog timer The hardware watchdog timer (WDT) resets the UPSD323xx devices when it overflows. The WDT is intended as a recovery method in situations where the CPU may be subjected to a software upset. To prevent a system reset the timer must be reloaded in time by the application software ...
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... Bit Symbol 7 — WDRST6 WDRST0 1. The Watchdog Timer (WDT) is enabled at power-up or reset and must be served or disabled. 58/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Reset pulse width (about 10ms at 40Mhz, about 50ms at 8Mhz) Reset period (1.258 second at 40Mhz) (about 6.291 seconds at 8Mhz WDRST5 WDRST4 ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Timer/counters (Timer 0, Timer 1 and Tim- 11 Timer/counters (Timer 0, Timer 1 and Timer 2) The UPSD323xx devices has three 16-bit Timer/Counter registers: Timer 0, Timer 1 and Timer 2. All of them can be configured to operate either as timers or event counters and are compatible with standard 8032 architecture. ...
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... TMOD register (TMOD Gate C/T 60/189 UPSD3234A, UPSD3234BV, UPSD3233B, Interrupt 0 Edge Flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed Interrupt 0 Type Control Bit. Set/cleared by software to specify falling- edge/low-level triggered external interrupt Figure 21 shows the Mode 0 operation as it applies to Timer ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Timer/counters (Timer 0, Timer 1 and Tim- Table 39. Description of the TMOD bits Bit Symbol 7 Gate 6 C Gate 2 C 11.1.3 Mode 2 Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure 22. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset by software ...
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... If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input T2EX will also trigger the 16-bit reload 62/189 UPSD3234A, UPSD3234BV, UPSD3233B, Figure 23. TL0 uses the Timer 0 control Bits: C/T, GATE, TR0, INT0, ÷ ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Timer/counters (Timer 0, Timer 1 and Tim- and set EXF2. Auto-reload mode is illustrated in the Standard Serial Interface (UART) Figure 25. The Baud Rate Generation mode is selected by (RCLK, RCLK1)=1 and/or (TCLK, TCLK1)= described in conjunction with the serial port. Table 40. Timer/counter 2 control register (T2CON) ...
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... Extra External Interrupt ¯ (Timer Timer 2 stops ÷ TL2 (8 bits) C/ Control TR2 Capture RCAP2L RCAP2H Control EXEN2 UPSD3234A, UPSD3234BV, UPSD3233B, Input clock Remarks Internal f /12 OSC f /12 OSC f /12 OSC — TH2 TF2 (8 bits) EXP2 External (P1.0/T2) MAX f /24 ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Timer/counters (Timer 0, Timer 1 and Tim- Figure 25. Timer 2 in Auto-Reload mode f OSC T2 pin Transition Detector T2EX pin ÷ TL2 (8 bits) C/ Control TR2 Reload RCAP2L RCAP2H Control EXEN2 TH2 TF2 (8 bits) Timer 2 Interrupt EXP2 AI06626 65/189 ...
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... Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a Stop bit. The port can be programmed such that when the Stop bit is received, the serial port interrupt will 66/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV . OSC ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV be activated only if RB8 = 1. This feature is enabled by setting Bit SM2 in SCON. A way to use this feature in multi-processor systems is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is ' address byte and data byte ...
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... TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. 68/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Transmit Interrupt Flag. Set by hardware at the end of the 8th bit time in Mode the beginning of the Stop bit in the other modes, in any serial transmission ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Now, the baud rates in Modes 1 and 3 are determined at Timer 2’s overflow rate as follows: Modes 1 and 3 Baud Rate = Timer 2 Overflow Rate / 16 Table 45. Timer 1-generated commonly used baud rates Baud Rate Mode 0 Max: 1MHz Mode 2 Max: 375K Modes 1, 3: 62.5K 19 ...
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... The transmission begins with activation of SEND which puts the start bit at TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. 70/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the '1' that was initially loaded into the 9th position is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after “ ...
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... If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the RxD input. 72/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 26. Serial port Mode 0 block diagram Write to SBUF S6 REN R1 Figure 27. Serial port Mode 0 waveforms Write to SBUF Send Shift RxD (Data Out) TxD (Shift Clock) Write to SCON Receive Shift RxD (Data In) TxD (Shift Clock) Internal Bus SBUF CL Zero Detector ...
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... SMOD 0 TCLK 0 RCLK Figure 29. Serial port Mode 1 waveforms Tx Clock Write to SBUF Send Data Shift TxD T1 Rx Clock RxD Bit Detector Sample Times Shift RI 74/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Timer2 Overflow TB8 Write to SBUF Start ÷16 Tx Clock Serial 1 Port Interrupt ÷16 Sample ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 30. Serial port Mode 2 block diagram Phase2 Clock 1/2*f OSC ÷ SMOD Figure 31. Serial port Mode 2 waveforms Tx Clock Write to SBUF Send Data Shift TxD TI Stop Bit Generator Rx Clock RxD Bit Detector Sample Times Shift RI TB8 Write to SBUF ...
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... TCLK 0 RCLK Figure 33. Serial port Mode 3 waveforms Tx Clock Write to SBUF Send Data Shift TxD TI Stop Bit Generator Rx Clock RxD Bit Detector Sample Times Shift RI 76/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Timer2 Overflow TB8 Write to SBUF Start ÷16 Tx Clock Serial 1 Port Interrupt ÷16 ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 13 Analog-to-digital convertor (ADC) The analog to digital (A/D) converter allows conversion of an analog input to a corresponding 8-bit digital value. The A/D module has four analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation ...
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... ACON Table 47. Description of the ACON bits Bit Symbol — 5 ADEN 4 — ADS1, ADS0 ADST 78/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Ladder Resistor ecode D Input MUX S/H INTERNAL BUS Bit register name ADAT5 ADAT4 ADAT3 ADAT2 ADEN ADS1 ADS0 Reserved 0 : ADC shut off and consumes no operating current ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 47. Description of the ACON bits (continued) Bit Symbol 0 ADSF Table 48. ADC clock input MCU clock frequency 40MHz 36MHz 24MHz 12MHz 0 : A/D conversion is in process ADC Status bit A/D conversion is completed, not in process Prescaler register value Analog-to-digital convertor (ADC) ...
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... The repetition frequency of the PWM output is given by: fPWM = (f 8 OSC And the input clock frequency to the PWM counters See Section 7: I/O ports (MCU module) pin as PWM output. 80/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV / prescaler0 256) for more information on how to configure the Port (prescaler data value + 1) OSC ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 35. Four-channel 8-bit PWM block diagram CPU rd/ OSC PWMCON bit5 (PWME) Table 49. PWM SFR memory map SFR Reg name addr 7 A1 PWMCON PWML PWMP PWME CFG4 A2 PWM0 A3 PWM1 A4 PWM2 A5 PWM3 AA PWM4P AB PWM4W B1 PSCL0L DATA BUS 8 8-bit PWM0-PWM3 ...
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... Period Register defines the period of the PWM. The input clock to the Prescaler is f /2. The PWM 4 channel is assigned to Port 4.7. OSC Figure 36. Programmable 4-channel PWM block diagram CPU RD/WR f OSC / 2 PWMCON Bit 5 (PWME) 82/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Bit register name DATA BUS 8 8 8-bit PWM4P ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 14.3 PWM 4-channel operation The 16-bit Prescaler1 divides the input clock (f clock runs the 8-bit Counter of the PWM 4 channel. The input clock frequency to the PWM 4 Counter is: f PWM4 = (f OSC When the Prescaler1 Register (B4h, B3h) is set to data value '0,' the maximum input clock frequency to the PWM 4 Counter is f The PWM 4 Counter is a free-running, 8-bit counter ...
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... SxDAT: data shift register. ● SxADR: slave address register. Slave address recognition is performed by On-Chip H/W. Figure 38. Block diagram of the I 84/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 2 C ports implemented in the UPSD323xx devices. 2 C-bus, consists of a data line (SDAx) and a clock line 2 C bus serial I/O ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 50. Serial control register (SxCON: S1CON, S2CON CR2 ENII Table 51. Description of the SxCON bits Bit Symbol 7 CR2 6 ENII 5 STA 4 STO 3 ADDR CR1 0 CR0 Table 52. Selection of the serial clock frequency SCL in Master mode CR2 CR1 STA STO ADDR ...
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... SxDAT contains the serial data to be transmitted or data which has just been received. The MSB (Bit 7) is transmitted or received first; that is, data shifted from right to left. Table 53. Serial status register (SxSTA STOP 86/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV f OSC CR0 divisor 12 MHz 0 480 12.5 ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 54. Description of the SxSTA bits Bit Symbol STOP 5 INTR 4 TX_MODE 3 BBUSY 2 BLOST 1 /ACK_REP 0 SLV 1. Interrupt Flag bit (INTR, SxSTA Bit 5) is cleared by Hardware as reading SxSTA register interrupt flag (INTR) can occur in below case. (except DDC2B mode at SWENB=0) Table 55 ...
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... OSC 20MHz (f /2 -> 100ns) OSC 8MHz (f /2 -> 250ns) OSC 88/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Register Reset Name Value To control the start/stop hold time detection for the S1SETUP 00h DDC module in Slave mode To control the start/stop hold time detection for the ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 16 DDC interface The basic DDC unit consists storage. The 8032 core is responsible of loading the contents of the SRAM with the DDC data. The DDC unit has the following features: ● Supports both DDC1 and DDC2b modes ● Features 256 bytes of DDC data - initialized by the 8032 core ● ...
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... EX_DAT N Table 61. Description of the DDCON register bits Bit Symbol 7 — 6 EX_DAT 5 SWENB 4 DDC_AX 90/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Bit Register Name SWEN DDC_A DDCIN DDC1EN Reserved 0 = The SRAM has 128 bytes (Default The SRAM has 256 bytes Note: This bit is valid for DDC1 & DDC2b modes 0 = Data is automatically read from SRAM at the current location of DDCADR and sent out via current DDC protocol ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 61. Description of the DDCON register bits (continued) Bit Symbol 3 DDC1_Int 2 DDC1EN 1 SWHINT 0 Mode Table 62. SWNEB bit function DDC1 or DDC2b mode Disabled SWENB DDCCON.bit2 = 0 (DDC1 mode Disable) or S1CON.bit6 = this state, the DDC unit is disabled. The DDC SRAM cannot be accessed by the MCU. No MCU interrupt and no DDC activity will occur ...
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... In the initialization phase, 9 clock cycles on V synchronization. During this period, the SDA pin will be kept at high impedance state. If DDC1 hardware mode is used, the following procedure is recommended to proceed DDC1 operation. 92/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Communication isidle Is VSYNC present? EDID sent continously using VSYNC as clock ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 1. Reset DDC1 enable (by default, DDC1 enable is cleared as LOW after Power-on Reset). 2. Set SWENB as high (the default value is zero.) 3. Depending on the data size of EDID data, set EX_DAT as LOW (128 bytes) or HIGH (256 bytes using bulky moving commands (DDCADR, RAMBUF involved) to move the entire EDID data to RAM buffer ...
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... I inhibit the further action from the master. The transaction can be proceeded in either byte or burst format. Figure 42. Conceptual structure of the DDC interface 94/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 2 C interface. However, in the level of DDC2B protocol, SCL pin can be stretched low to ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 17 USB hardware The characteristics of USB hardware are as follows: ● Complies with the Universal Serial Bus specification Rev. 1.1 ● Integrated SIE (Serial Interface Engine), FIFO memory and transceiver ● Low speed (1.5Mbit/s) device capability ● Supports control endpoint0 and interrupt endpoint1 and 2 ● ...
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... Bit Symbol 7 SUSPND 6 — 5 RSTF 96/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV R/W USB Function Enable Bit. When USBEN is clear, the USB module will not respond to R/W any tokens from host. RESET clears this bit. Specify the USB address of the device. R/W RESET clears these bits. ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 68. Description of the UISTA bits (continued) Bit Symbol 4 TXD0F 3 RXD0F 2 TXD1F 1 EOPF 0 RESUMF Table 69. USB Endpoint0 transmit control register (UCON0: 0EAh TSEQ0 STALL0 R/W Endpoint0 Data Transmit Flag. This bit is set after the data stored in Endpoint 0 transmit buffers has been sent and an ACK handshake packet from the host is received ...
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... USB Endpoint1 (and 2) transmit control register (UCON1: 0EBh TSEQ1 EP12SEL 98/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV R/W Endpoint0 Data Sequence Bit. (0=DATA0, 1=DATA1) This bit determines which type of data packet (DATA0 or R/W DATA1) will be sent during the next IN transaction. Toggling of this bit must be controlled by software. RESET clears this bit Endpoint0 Force Stall Bit ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 72. Description of the UCON1 bits Bit Symbol 7 TSEQ1 6 EP12SEL 5 TX1E 4 FRESUM TP1SIZ3 TP1SIZ0 Table 73. USB control register (UCON2: 0ECh — — Table 74. Description of the UCON2 bits Bit Symbol — 4 SOUT 3 EP2E R/W Endpoint 1/ Endpoint 2 Transmit Data Packet PID. (0=DATA0, ...
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... OSC Note: USB works ONLY with the MCU Clock frequencies of 12, 24 MHz. The Prescaler values for these frequencies are 0, 1, and 2. 100/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV R/W R/W Endpoint1 enable. RESET clears this bit R/W Endpoint2 Force Stall Bit. RESET clears this bit R/W Endpoint1 Force Stall Bit ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 80. USB SFR memory map SFR Reg Add Name USCL E6 UDT1 UDT1.7 UDT1.6 UDT1.5 UDT1.4 UDT1.3 UDT1.2 UDT1.1 E7 UDT0 UDT0.7 UDT0.6 UDT0.5 UDT0.4 UDT0.3 UDT0.2 UDT0.1 E8 UISTA SUSPND — SUSPNDI E9 UIEN RSTE E EA UCON0 TSEQ0 STALL0 EP12SE ...
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... V to 3.8 V with respect to its local ground reference without damage. In addition to the differential receiver, there is a single-ended receiver for each of the two data lines. The single-ended receivers have a switching threshold between 0.8 V and 2.0 V (TTL inputs). 102/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV One Bit Time 1.5 Mb/s Signal pins ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 44. Differential input sensitivity over entire common mode range 1.0 0.8 0.6 0.4 0.2 0.0 17.4 External USB pull-up resistor The USB system specifies a pull-up resistor on the D- pin for low-speed peripherals. The USB Spec 1.1 describes a 1.5 kΩ pull-up resistor to a 3.3 V supply. An approved alternative method is a 7.5 kΩ ...
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... External Bus Pull- Resistance, D- External Bus Pull-down R PD Resistance ± 10 Level guaranteed for range With RPU, external idle resistor, 7.5 κ±2 104/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Crossover Crossover Point Extended Point Diff. Data to SE0 Skew N*T +T PERIOD DEOP Crossover Points Consecutive ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 82. Transceiver AC characteristics Symb tDRATE Low Speed Data Rate tDJR1 Receiver Data Jitter Tolerance tDJR2 Differential Input Sensitivity Differential to EOP Transition tDEOP Skew tEOPR1 EOP Width at Receiver tEOPR2 EOP Width at Receiver tEOPT Source EOP Width tUDJ1 Differential Driver Jitter ...
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... CPU core activity and put the PSD module into Power-down mode. ● Erase/WRITE cycles: Flash memory - 100,000 minimum PLD - 1,000 minimum Data Retention: 15 year minimum (for Main Flash memory, Boot, PLD and Configuration bits) 106/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 49 shows the functional blocks in the ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 49. UPSD323xx PSD module block diagram 18.2 In-system programming (ISP) Using the JTAG signals on Port C, the entire PSD module device can be programmed or erased without the use of the MCU. The primary Flash memory can also be programmed in- system by the MCU executing the programming algorithms out of the secondary memory, or SRAM ...
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... Table 83. Methods of programming different functional blocks of the PSD module Functional Block Primary Flash memory Secondary Flash memory PLD array (DPLD and CPLD) PSD module configuration 108/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV JTAG programming Device programmer Yes Yes Yes Yes Yes Yes Yes ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 19 Development system UPSD323xx devices are supported by PSDsoft, a Windows-based software development tool (Windows-95, Windows-98, Windows-NT). A PSD module design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD module pin functions and memory map information ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, (1) Description Reads Port pin as input, MCU I/O Input mode Selects mode between MCU I/O or Address Out Stores data for output to Port pins, MCU I/O Output mode Configures Port pin as input or output Configures Port pins as either CMOS or Open Drain on some pins, while selecting high slew rate on other pins ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 21 PSD module detailed operation As shown in Figure ● Memory blocks ● PLD blocks ● I/O Ports ● Power Management Unit (PMU) ● JTAG Interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. ...
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... The MCU can execute a specific Flash memory instruction that consists of several WRITE and READ operations. This involves writing specific data patterns to special addresses within the Flash memory to invoke an embedded algorithm. These instructions are summarized in 112/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 85. Section 23: ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Typically, the MCU can read Flash memory using READ operations, just as it would read a ROM device. However, Flash memory can only be altered using specific Erase and Program instructions. For example, the MCU cannot write a single byte directly to Flash memory as it would write a byte to RAM ...
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... Sector Protection Status when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle. 19. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode. 114/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Cycle 1 Cycle 2 Cycle 3 ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 20. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is intended. The MCU must retrieve, for example, the code from the secondary Flash memory when reading the Sector Protection Status of the primary Flash memory. ...
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... In case of an error in a Flash memory Sector Erase or Byte Program cycle, the Flash memory sector in which the error occurred or to which the programmed byte belongs must no longer be used. Other Flash memory sectors may still be used. The Error Flag bit (DQ5) is reset after a Reset Flash instruction. 116/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 22.5.7 Erase time-out flag (DQ3) The Erase Time-out Flag bit (DQ3) reflects the time-out period allowed between two consecutive Sector Erase instructions. The Erase Time-out Flag bit (DQ3) is reset to '0' after a Sector Erase cycle for a time period of 100µs + 20% unless an additional Sector Erase instruction is decoded. After this time period, or when the additional Sector Erase instruction is decoded, the Erase Time-out Flag bit (DQ3) is set to ‘ ...
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... The Error Flag bit (DQ5) is set if either an internal time-out occurred while the embedded algorithm attempted to program the byte the MCU attempted to program a ' bit that was not erased (not erased is logic '0'). 118/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 51 START READ DQ5 & DQ7 ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the byte that was written to Flash memory with the byte that was intended to be written. When using the Data Toggle method after an Erase cycle, Flag bit (DQ6) toggles until the Erase cycle is complete the Error Flag bit (DQ5) indicates a time-out condition on the Erase cycle ...
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... Select (FS0-FS7 or CSBOOT0-CSBOOT3) is High. (See data from another Flash memory sector after the Erase cycle has been suspended. 120/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 85. If any byte of the Bulk Erase instruction is memory. The Error Flag bit (DQ5) returns a '1' if there has memory ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Suspend Sector Erase is accepted only during an Erase cycle and defaults to READ mode. A Suspend Sector Erase instruction executed during an Erase time-out period, in addition to suspending the Erase cycle, terminates the time out period. The Toggle Flag bit (DQ6) stops toggling when the internal logic is suspended. The status of this bit must be monitored at an address within the Flash memory sector being erased. The Toggle Flag bit (DQ6) stops toggling between 0.1µ ...
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... The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to two product terms, allowing flexible memory mapping. 122/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Bit 5 Bit Primary Flash memory or secondary Flash memory Sector <i> is not write-protected. ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 22.10 Sector Select and SRAM Select Sector Select (FS0-FS7, CSBOOT0-CSBOOT3) and SRAM Select (RS0) are all outputs of the DPLD. They are setup by writing equations for them in PSDsoft Express. The following rules apply to the equations for these signals: 1 ...
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... Flash memory, secondary Flash memory, and SRAM to be accessed by either Program Select Enable (PSEN) or READ Strobe (RD). For example, to configure the primary Flash memory in Combined space, Bits b2 and b4 of the VM Register are set to '1' (see Figure 55). 124/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Highest Priority Level 1 SRAM, I/O, or Peripheral I/O Level 2 Secondary ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 54. Separate Space mode Figure 55. Combined Space mode RD VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 VM REG BIT 2 VM REG BIT 0 22.11 Page register The 8-bit Page Register increases the addressing capability of the MCU Core by a factor 256 ...
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... Memory blocks Figure 56. Page register 126/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV RESET PGR0 PGR1 PGR2 DPLD PGR3 AND PGR4 CPLD PGR5 PGR6 PGR7 PAGE PLD REGISTER INTERNAL PSD MODULE SELECTS AND LOGIC AI05799 ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 23 PLDs PLDs bring programmable logic functionality to the UPSD. After specifying the logic for the PLDs using PSDsoft Express, the logic is programmed into the device and available upon Power-up. Table 90. DPLD and CPLD Inputs Input Source MCU Address Bus ...
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... SRAM Select (RS0) signal (two product terms) ● 1 internal CSIOP Select signal (selects the PSD module registers) ● 2 internal Peripheral Select signals (Peripheral I/O mode). 128/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV for details on how to set the Turbo Bit. 8 PAGE REGISTER DECODE PLD ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 91. DPLD logic array I /O PORTS (PORT A,B,C) 1 MCELLAB.FB [7:0] (FEEDBACKS) MCELLBC.FB [7:0] (FEEDBACKS) PGR0 - PGR7 2:1 ] PDN (APD OUTPUT) PSEN, RD, WR, ALE 2 2 RESET RD_BSY 1. Port A inputs are not available in the 52-pin package 2. Inputs from the MCU module 23 ...
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... PSDsoft. The flip-flop’s clock, preset, and clear inputs may be driven from a product term of the AND Array. Alternatively, CLKIN (PD1) can be used for the clock input to the flip- 130/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV MCU ADDRESS / DATA BUS FROM OTHER MACROCELLS ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV flop. The flip-flop is clocked on the rising edge of CLKIN (PD1). The preset and clear are active High inputs. Each clear input can use up to two product terms. Table 92. Output macrocell port and data bit assignments Output Assignment Macrocell ...
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... Output enable of the OMC The Output Macrocells (OMC) block can be connected to an I/O port pin as a PLD output. The output enable of each port pin driver is controlled by a single product term from the 132/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Section 24: I/O ports (PSD MASK REG. ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV AND Array, ORed with the Direction Register output. The pin is enabled upon Power- output enable equation is defined and if the pin is declared as a PLD output in PSDsoft Express. If the Output Macrocell (OMC) output is declared as an internal node and not as a port pin output in the PSDabel file, the port pin can be used for other I/O functions ...
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... The Port Data Buffer (PDB) is connected to the Internal Data Bus for feedback and can be read by the MCU. The Data Out and macrocell outputs, Direction and Control Registers, and port pin input are all connected to the Port Data Buffer (PDB). 134/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 63 to Figure 66 ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 61. General I/O port architecture WR ADDRESS ALE MACROCELL OUTPUTS EXT ENABLE PRODUCT TERM ( .OE ) The Port pin’s tri-state output driver enable is controlled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction Register. If ...
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... JTAG in-system programming (ISP) Port C is JTAG compliant, and can be used for In-System Programming (ISP). For more information on the JTAG Port, see interface. 136/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 61. Section 27: Programming in-circuit using the JTAG serial Table 84. Section 24.6: Peripheral ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 62. Peripheral I/O mode Table 93. Port operating modes Port mode MCU I/O PLD I/O McellAB Outputs McellBC Outputs Additional Ext. CS Outputs PLD Inputs Address Out Peripheral I/O JTAG ISP 1. Port A is not available in the 52-pin package pins PC2, PC3, PC4, and PC7 only. ...
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... Table 100 shows the Drive Register for Ports and D. It summarizes which pins can be configured as Open Drain outputs and which pins the slew rate can be set for. 138/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 84. The addresses in Table 96, are used for setting the Port ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 96. Port configuration registers (PCR) Register Name Control Direction (1) Drive Select Note: 1. See Table 100 for Drive Register Bit definition. Table 97. Port pin direction control, output enable P.T. not defined Direction Register Bit Table 98. Port pin direction control, output enable P.T. defined ...
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... Drain (1) Port Not Applicable. Table 101. Port data registers Register Name Data In Data Out Output Macrocell Mask Macrocell Input Macrocell Enable Out 140/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Bit 6 Bit 5 Bit 4 Open Open Open Drain Drain Drain Open Open Open Drain Drain ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 24.10 Ports A and B – functionality and structure Ports A and B have similar functionality and structure, as shown in can be configured to perform one or more of the following functions: ● MCU I/O mode ● CPLD Output – Macrocells McellAB7-McellAB0 can be connected to Port A or Port B. ...
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... CLKIN (PD1) as input to the macrocells flip-flops and APD counter ● PSD Chip Select Input (CSI, PD2). Driving this signal High disables the Flash memory, SRAM and CSIOP. 142/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DATA OUT REG. DATA OUT SPECIAL FUNCTION ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 65. Port D structure 24.13 External chip select The CPLD also provides two External Chip Select (ECS1-ECS2) outputs on Port D pins that can be used to select external devices. Each External Chip Select (ECS1-ECS2) consists of one product term that can be configured active High or Low. The output enable of the pin is controlled by either the output enable product term or the Direction register ...
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... I/O ports (PSD module) Figure 66. Port D external chip select signals 144/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV ENABLE (.OE) PT1 POLARITY BIT ENABLE (.OE) PT2 POLARITY BIT DIRECTION REGISTER PD1 PIN ECS1 DIRECTION REGISTER PD2 PIN ECS2 AI06607 ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 25 Power management All PSD modules offer configurable power saving options. These options may be used individually or in combinations, as follows: ● The primary and secondary Flash memory, and SRAM blocks are built with power management technology. In addition to using special silicon design methodology, power management technology puts the memories into Standby mode when address/data inputs are not changing (zero DC current) ...
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... I/O to “wake-up” before their outputs can change. See for Power-down mode effects on PSD module ports. ● Typical standby current is of the order of microamperes. These standby current values assume that there are no transitions on any PLD input. 146/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV TRANSITION DETECTION PD CLR APD ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Other power-saving options The PSD module offers other reduced power saving options that are independent of the Power-down mode. Except for the PSD Chip Select Input (CSI, PD2) features, they are enabled by setting bits in PMMR0 and PMMR2. Figure 68. Enable Power-down flowchart Table 102. Power-down mode’ ...
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... PLD Array Bit 4 clk PLD MCell Bit 5 clk Bit 6 X Bit 7 X 148/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 0 Not used, and should be set to zero off Automatic Power-down (APD) is disabled Automatic Power-down (APD) is enabled. 0 Not used, and should be set to zero PLD Turbo mode is on PLD Turbo mode is off, saving power ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 104. Power management mode registers (PMMR2) Bit 0 X Bit 1 X PLD Array Bit 2 WR PLD Array Bit 3 RD PLD Array Bit 4 PSEN PLD Array Bit 5 ALE Bit 6 X Bit The bits of this register are cleared to zero following Power-up. Subsequent RESET pulses do not clear the registers ...
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... Program or Erase cycle, Reset (RESET) terminates the cycle and returns the Flash memory to the READ mode within a period of t Figure 69. Reset (RESET) timing V CC RESET 150/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV is below The same t period is needed before the device is operational NLNH OPR Figure 69 shows the timing of the Power-up and Warm RESET ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 106. Status during Power-on RESET, Warm RESET and Power-down mode Port Configuration MCU I/O PLD Output Address Out Peripheral I/O Register PMMR0 and PMMR2 Macrocells flip-flop status (1) VM Register All other registers 1. The SR_cod and Periphmode Bits in the VM Register are always cleared to '0' on Power-on RESET or Warm RESET ...
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... Programming in-circuit using the JTAG serial interface UPSD3234A, UPSD3234BV, UPSD3233B, 27 Programming in-circuit using the JTAG serial interface The JTAG Serial Interface pins (TMS, TCK, TDI, and TDO) are dedicated pins on Port C (see Table 107). All memory blocks (primary and secondary Flash memory), PLD logic, and PSD module Configuration Register Bits may be programmed through the JTAG Serial Interface block ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV scan the status out serially using the standard JTAG channel. See Application Note AN1153. TERR indicates if an error has occurred when erasing a sector or programming a byte in Flash memory. This signal goes Low (active) when an Error condition occurs, and stays Low until an “ ...
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... When delivered from ST, the UPSD323xx devices have all bits in the memory and PLDs set to '1.' The code, configuration, and PLD logic are loaded using the programming procedure. Information for programming the device is available directly from ST. Please contact your local sales representative. 154/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 29 AC/DC parameters These tables describe the AD and DC parameters of the UPSD323xx devices: ● DC Electrical Specification ● AC Timing Specification ● PLD Timing – Combinatorial Timing – Synchronous Clock mode – Asynchronous Clock mode – Input Macrocell Timing ● MCU module Timing – ...
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... Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory access % SRAM access % I/O access Operational modes % Normal % Power-down mode Number of product terms used (from fitter report total product terms Turbo mode 156/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV /frequency consumption (3 V range ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 108. PSD module example, typ. power calculation at V off) (continued %pwrdown total CC I total = 20mA x 40% + 28.45mA x 40% + 250µA x 60% CC This is the operating power with no Flash memory Erase or Program cycles in progress. Calculation is based on all I/O pins being disconnected and I ...
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... IO V Supply Voltage CC V Device Programmer Supply Voltage PP V Electrostatic Discharge Voltage (Human Body Model) ESD 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 Ω, R2=500 Ω) 158/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Parameter (1) or Hi- Min. Max. Unit –65 125 °C 235 °C – ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 31 EMC characteristics Susceptibility test are performed on a sample basis during product characterization. 31.1 Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs) ...
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... Class description: A Class is an STMicroelectronics internal specification. All of its limits are higher than the JEDEC specifications. This means when a device belongs to “Class A,” it exceeds the JEDEC standard. “Class B” strictly covers all of the JEDEC criteria (International standards). 160/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV (Table 111). This test complies with the JESD22-A114A Standard. Parameter ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 32 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...
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... PLD Turbo mode Off) Idle current, typical (CPU halted but some peripherals active; 25°C operation; 45 PLD product terms used; PLD Turbo mode Off) 162/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Time Logic Level Low or ALE Logic Level High Valid No Longer a Valid Logic Level Float Pulse Width ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 117. Major parameters (continued) Parameters/conditions/ comments Standby current, typical (Power-down mode, requires reset to exit mode; without Low-Voltage Detect (LVD) Supervisor) I/O sink/source current Ports and D PLD macrocells (For registered or combinatorial logic) PLD inputs (Inputs from pins, macrocell feedback, or ...
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... Program Logic '0' input current I IL (Ports 1,2,3,4) Logic 1-to-0 transition I TL current (Ports 1,2,3,4) Reset pin pull-up current I RST (RESET) 164/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Test conditions (in Parameter addition to those in Table 113) 4.5 V < 4.5 V < 4.5 V < 4.5 V < 4.5 V < ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 118. DC characteristics (5 V devices) (continued) Symbol XTAL feedback resistor I FR current (XTAL1) I Input leakage current LI I Output leakage current LO (1) I Power-down mode PD Active (12 MHz) Idle (12 MHz) Active (24 MHz) I CC_CPU (2,3,6) Idle (24 MHz) Active (40 MHz) Idle (40 MHz) ...
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... Reset pin pull-up current I RST (RESET) XTAL feedback resistor I FR current (XTAL1) I Input leakage current LI I Output leakage current LO 166/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Test conditions (in Parameter addition to those in Table 114) 3.0 V < 3.0 V < 3.0 V < 3.0 V < 3.0 V < V ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 119. DC characteristics (3 V devices) (continued) Symbol (1) I Power-down mode PD Active (12 MHz) Idle (12 MHz) I CC_CPU (2,3,6) Active (24 MHz) Idle (24 MHz) I Operating CC_PSD (6) (DC) supply current PLD AC base I CC_PSD Flash memory AC adder (6) (AC) SRAM AC adder 1. I (Power-down mode) is measured with: ...
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... Address float to PSEN AZPL 1. Conditions (in addition to those in output is 100 pF Interfacing the UPSD323xx devices to devices with float times permissible. This limited bus contention does not cause any damage to Port 0 drivers. 168/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV t LLPL t LHLL t AVLL t PLPH t LLIV t PLIV t LLAX ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 121. External program memory AC characteristics (with the 3 V MCU module) Symbol t ALE pulse width LHLL t Address set-up to ALE AVLL t Address hold after ALE LLAX t ALE Low to valid instruction in LLIV t ALE to PSEN LLPL t PSEN pulse width PLPH ...
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... V devices) Figure 74. External data memory Read cycle ALE PSEN RD PORT 0 PORT 2 Figure 75. External data memory Write cycle ALE PSEN WR PORT 0 PORT 2 170/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 24 MHz oscillator (1) Parameter Min. Table 114 3.0 to 3.6 V tLHLL tLLDV tLLWL tRLRH tRLDV ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 124. External data memory AC characteristics (with the 5 V MCU module) Symbol t RD pulse width RLRH t WR pulse width WLWH t Address hold after ALE LLAX2 valid data in RHDX t Data hold after RD RHDX t Data float after RD RHDZ t ALE to valid data in ...
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... Overall accuracy IN N Non-linearity error NLE N Differential non-linearity error DNLE N Zero-offset error ZOE N Full scale error FSE N Gain error GE t Conversion time CONV 172/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 24 MHz oscillator (1) Parameter Min. 180 180 170 15 Table 114 3.0 to 3.6 V Test Parameter ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 76. Input to output disable / enable Table 127. CPLD combinatorial timing (5 V devices) Symbol CPLD input pin/feedback to ( CPLD combinatorial output CPLD input to CPLD output t EA enable CPLD input to CPLD output t ER disable CPLD register clear or t ARP preset delay ...
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... Clock to output delay CO t CPLD array delay ARD t Minimum clock period MIN 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. 2. CLKIN (PD1) t CLCL 174/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV t CH CLKIN INPUT REGISTERED OUTPUT Parameter Conditions 1/( ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 130. CPLD macrocell synchronous clock mode timing (3 V devices) Symbol Maximum frequency external feedback Maximum frequency f MAX internal feedback (f Maximum frequency pipelined data t Input setup time S t Input hold time H t Clock high time CH t Clock low time ...
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... SA t Input hold time HA t Clock input high time CHA t Clock input low time CLA t Clock to output delay COA t CPLD array delay ARD t Minimum clock period MINA 176/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Conditions Min 1/( COA 1/(t +t – SA COA ) 10) CNTA 1/( CHA CLA ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 80. Input macrocell timing (product term clock) Table 133. Input macrocell timing (5 V devices) Symbol t Input setup time IS t Input hold time IH t NIB input high time INH t NIB input low time INL t NIB input to combinatorial delay INO 1 ...
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... Sector Erase Time-Out WHWLO DQ7 Valid to Output (DQ7-DQ0) Valid (Data t Q7VQV Polling) 1. Programmed to all zero before erase. 2. The polling status, DQ7, is valid t 178/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Parameter (1) (pre-programmed) (2) time units before the data byte, DQ0-DQ7, is valid for reading. Q7VQV Parameter (1) ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 81. Peripheral I/O Read timing ALE A /D BUS CSI RD Table 137. Port A peripheral data mode Read timing (5 V devices) Symbol t Address valid to data valid AVQV–PA t CSI valid to data valid SLQV– data valid RLQV–PA t Data in to data out valid DVQV– ...
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... WLQV–PA t Data to Port A data propagation delay DVQV– invalid to Port A tri-state WHQZ–PA 1. Data stable on Port 0 pins to data on Port A. Figure 83. Reset (RESET) timing V CC RESET 180/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV ADDRESS tWLQV (PA) Parameter Parameter V (min NLNH-PO t OPR Power-On Reset DATA OUT ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 141. Reset (RESET) timing (5 V devices) Symbol t RESET active low time NLNH t Power-on reset active low time NLNH–PO t Warm RESET NLNH–A t RESET high to operational device OPR 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. ...
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... For non-PLD Programming, Erase or in ISC By-pass mode. 2. For Program or Erase PLD only. Figure 85. MCU module AC measurement I/O waveform 1. AC inputs during testing are driven Timing measurements are made at V 182/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Parameter Conditions (Note 1) (Note 1) (Note 1) (Note 2) ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 86. PSD module AC float I/O waveform 1. For timing purposes, a Port pin is considered longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded V ≥ 20mA 2. I and Figure 87. External clock cycle Figure 88. Recommended oscillator circuits 1. C1 ± ...
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... Table 145. Capacitance Symbol C Input capacitance (for input pins) IN Output capacitance (for C OUT input/output pins) 1. Sampled only, not 100% tested. 2. Typical values are for T 184/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 2.01 V 195 Ω Device Under Test (Including Scope and Jig Capacitance) Parameter Test conditions ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 33 Package mechanical information Figure 91. LQFP52 – 52-lead plastic thin, quad, flat package outline Pin 1 identification 1. Drawing is not to scale. Table 146. LQFP52 – 52-lead plastic thin, quad, flat package mechanical data Symbol ddd 1. Values in inches are converted from mm and rounded to 4 decimal digits. ...
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... C D 14.000 D1 12.000 D3 9.500 E 14.000 E1 12.000 E3 9.500 e 0.500 L 0.600 L1 1.000 k ccc 1. Values in inches are converted from mm and rounded to 4 decimal digits. 186/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Pin 1 identification 1 20 millimeters Min Max 1.600 0.050 0.150 1.350 1.450 0.170 0.270 ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 34 Part numbering Table 148. Ordering information scheme Example: Device type UPSD = Microcontroller PSD Family 3 = 8032 core PLD size Macrocells SRAM Size Kbytes Main Flash memory size Kbytes 3 = 128 Kbytes 4 = 256 Kbytes IP mix USB PWM, DDC, ADC, (2) UARTs, ...
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... November 2002 27-Feb-03 03-Sep-03 04-Feb-04 05-Jul-04 04-Nov-04 21-Jan-2009 188/189 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Revision 1.0 First Issue Updates: product information (Figure 3, 4, Table 1, 2); port information (Figure 17, 18, Table 30); interface information (Figure 30, 1.1 Table 44); remove programming guide; PSD module information (Figure 50, 51, Table 85); PLD information (Figure 58, 59, Table 91, 92, 93) ...
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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...