IC MCU OTP 8BIT 1K 16SOIC

COP8SAA716M9

Manufacturer Part NumberCOP8SAA716M9
DescriptionIC MCU OTP 8BIT 1K 16SOIC
ManufacturerNational Semiconductor
SeriesCOP8™ 8SA
COP8SAA716M9 datasheet
 


Specifications of COP8SAA716M9

Core ProcessorCOP8Core Size8-Bit
Speed10MHzConnectivityMicrowire/Plus (SPI)
PeripheralsPOR, PWM, WDTNumber Of I /o12
Program Memory Size1KB (1K x 8)Program Memory TypeOTP
Ram Size64 x 8Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 V
Oscillator TypeInternalOperating Temperature0°C ~ 70°C
Package / Case16-SOIC (0.300", 7.5mm Width)Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Eeprom Size-Data Converters-
Other names*COP8SAA716M9
COP8SAA716M9B
  
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COP8SA Family
8-Bit CMOS ROM Based and One-Time Programmable
(OTP) Microcontroller with 1k to 4k Memory, Power On
Reset, and Very Small Packaging
General Description
Note: COP8SAx devices are instruction set and pin com-
patible supersets of the COP800 Family devices, and are
replacements for these in new designs when possible.
The COPSAx Rom based and OTP microcontrollers are
highly integrated COP8
feature core devices, with 1k to 4k
memory and advanced features including low EMI. These
single-chip CMOS devices are suited for low cost applica-
tions requiring a full featured controller, low EMI, and POR.
100% form-fit-function compatible OTP versions are avail-
able with 1k, 2k, and 4k memory, and in a variety of pack-
ages including 28-pin CSP. Erasable windowed versions are
available for use with a range of COP8 software and hard-
ware development tools.
Memory
Device
(bytes)
COP8SAA5
1k ROM
COP8SAB5
2k ROM
COP8SAC5
4k ROM
COP8SAA7
1k OTP EPROM
COP8SAB7
2k OTP EPROM
COP8SAC7
4k OTP EPROM
COP8SAC7-Q3
4k EPROM
COP8SAC7-J3
4k EPROM
Key Features
n Low cost 8-bit OTP microcontroller
n OTP program space with read/write protection (fully
secured)
n Quiet Design (low radiated emissions)
n Multi-Input Wakeup pins with optional interrupts
(4 to 8 pins)
n 8 bytes of user storage space in EPROM
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUS
, COP8
, MICROWIRE
and WATCHDOG
iceMASTER
®
is a registered trademark of MetaLink Corporation.
© 2000 National Semiconductor Corporation
Family features include an 8-bit memory mapped architec-
ture, 10 MHz CKI with 1 µs instruction cycle, one multi-
function
16-bit
MICROWIRE/PLUS
IDLE modes, MIWU, idle timer, on-chip R/C oscillator, 12
high current outputs, user selectable options (WATCH-
DOG
, 4 clock/oscillator modes, power-on-reset), low EMI
2.7V to 5.5V operation, and 16/20/28/40/44 pin packages.
Devices included in this datasheet are:
RAM
I/O Pins
Packages
(bytes)
64
12/16/24
16/20/28 DIP/SOIC, 28 CSP
128
16/24
20/28 DIP/SOIC, 28 CSP
128
16/24/36/40
20/28 DIP/SOIC, 28 CSP,
40 DIP, 44 PLCC/QFP
64
12/16/24
16/20/28 DIP/SOIC, 28 CSP
128
16/24
20/28 DIP/SOIC, 28 CSP
128
16/24
20/28 DIP/SOIC, 28 CSP,
40 DIP, 44 PLCC/QFP
128
16/24/36
20/28/40 DIP
128
40
44 PLCC
n User selectable clock options
— Crystal/Resonator options
— Crystal/Resonator option with on-chip bias resistor
— External oscillator
— Internal R/C oscillator
n Internal Power-On Reset — user selectable
n WATCHDOG and Clock Monitor Logic — user selectable
n Up to 12 high current outputs
are trademarks of National Semiconductor Corporation.
DS012838
PRELIMINARY
November 2000
timer/counter
with
PWM
output,
serial I/O, two power saving HALT/
Temperature
0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
0 to +70˚C, -40 to +85˚C,
-40 to +125˚C
Room Temp. Only
Room Temp. Only
www.national.com

COP8SAA716M9 Summary of contents

  • Page 1

    ... OTP program space with read/write protection (fully secured) n Quiet Design (low radiated emissions) n Multi-Input Wakeup pins with optional interrupts ( pins bytes of user storage space in EPROM TRI-STATE ® registered trademark of National Semiconductor Corporation. MICROWIRE/PLUS , COP8 , MICROWIRE and WATCHDOG ™ ™ ™ iceMASTER ® ...

  • Page 2

    CPU Features n Versatile easy to use instruction set n 1 µs instruction cycle time n Eight multi-source vectored interrupts servicing — External interrupt — Idle Timer T0 — One Timer (with 2 interrupts) — MICROWIRE/PLUS Serial Interface — Multi-Input ...

  • Page 3

    General Description (Continued) Key features include an 8-bit memory mapped architecture, a 16-bit timer/counter with two associated 16-bit registers supporting three modes (Processor Independent PWM gen- eration, External Event counter, and Input Capture capabili- ties), two power saving HALT/IDLE modes ...

  • Page 4

    Connection Diagrams DS012838-2 Top View Top View www.national.com DS012838-3 Top View DS012838-39 Top View DS012838-5 FIGURE 2. Connection Diagrams 4 DS012838-4 Top View DS012838-6 Top View ...

  • Page 5

    ... Ordering Information 1k EPROM Temperature Order Number Package 0˚C to +70˚C COP8SAA716M9 16M COP8SAA720M9 20M COP8SAA728M9 28M COP8SAA716N9 16N COP8SAA720N9 20N COP8SAA728N9 28N −40˚C to +85˚C COP8SAA716M8 16M COP8SAA720M8 20M COP8SAA728M8 28M COP8SAA716N8 16N COP8SAA720N8 20N COP8SAA728N8 28N COP8SAA7SLB8 SLB −40˚C to +125˚ ...

  • Page 6

    ... Electrical Characteristics Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin DC Electrical Characteristics 0˚C T +70˚C unless otherwise specified. A Parameter Operating Voltage Power Supply Rise Time from 0.0V ...

  • Page 7

    DC Electrical Characteristics 0˚C T +70˚C unless otherwise specified. A Parameter Output Current Levels D Outputs Source Sink L Port Source (Weak Pull-Up) Source (Push-Pull Mode) Sink (L0–L3, Push-Pull Mode) Sink (L4–L7, Push-Pull Mode) All Others Source (Weak Pull-Up Mode) ...

  • Page 8

    AC Electrical Characteristics 0˚C T +70˚C unless otherwise specified. A Parameter Instruction Cycle Time ( Crystal/Resonator, External Internal R/C Oscillator R/C Oscillator Frequency Variation (Note 8) External CKI Clock Duty Cycle (Note 8) Rise Time (Note 8) Fall ...

  • Page 9

    ... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin ESD Protection Level DC Electrical Characteristics −40˚C T +85˚C unless otherwise specified. A Parameter Operating Voltage Power Supply Rise Time from 0.0V ...

  • Page 10

    DC Electrical Characteristics −40˚C T +85˚C unless otherwise specified. A Parameter Output Current Levels D Outputs Source Sink L Port Source (Weak Pull-Up) Source (Push-Pull Mode) Sink (L0–L3, Push-Pull Mode) Sink (L4–L7, Push-Pull Mode) All Others Source (Weak Pull-Up Mode) ...

  • Page 11

    AC Electrical Characteristics −40˚C T +85˚C unless otherwise specified. A Parameter Inputs t SETUP t HOLD Output Propagation Delay (Note 16 PD1 PD0 SO, SK All Others MICROWIRE Setup Time (t ) (Note 16) UWS MICROWIRE Hold ...

  • Page 12

    ... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin ESD Protection Level DC Electrical Characteristics −40˚C T +125˚C unless otherwise specified. A Parameter Operating Voltage Power Supply Rise Time from 0.0V ...

  • Page 13

    DC Electrical Characteristics −40˚C T +125˚C unless otherwise specified. A Parameter Allowable Sink Current per Pin (Note 17) D Outputs and All Others Maximum Input Current without Latchup (Note 15) RAM Retention Voltage Rise Time ...

  • Page 14

    Pin Descriptions COP8SAx I/O structure minimizes external component requirements. Software-switchable I/O enables designers to reconfigure the microcontroller’s I/O functions with a single instruction. Each individual I/O pin can be indepen- dently configured as an output pin low, an output ...

  • Page 15

    Pin Descriptions (Continued) FIGURE 5. I/O Port Configurations FIGURE 6. I/O Port Configurations — Output Mode FIGURE 7. I/O Port Configurations — Input Mode Port 8-bit output port that is preset high when RESET goes low. ...

  • Page 16

    Functional Description memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested. The accumu- lator (A) bits can also be directly and individually tested. RAM contents are undefined upon power-up. TABLE 1. ...

  • Page 17

    Functional Description 6.7 RESET The device is initialized when the RESET pin is pulled low or the On-chip Power-On Reset is enabled. FIGURE 8. Reset Logic The following occurs upon initialization: Port L: TRISTATE Port C: TRISTATE Port G: ...

  • Page 18

    Functional Description The contents of data registers and RAM are unknown fol- lowing the on-chip reset. FIGURE 10. Reset Timing (Power-On Reset Enabled) with V Tied to RESET CC DS012838-16 FIGURE 11. Reset Circuit Using Power-On Reset 6.8 OSCILLATOR ...

  • Page 19

    Functional Description With On-Chip Bias Resistor DS012838-17 DS012838-20 For operation at lower than maximum R/C oscillator frequency. (Continued) Without On-Chip Bias Resistor FIGURE 12. Crystal Oscillator DS012838-19 FIGURE 13. External Oscillator For operation at maximum R/C oscillator frequency. FIGURE ...

  • Page 20

    Functional Description 6.9 CONTROL REGISTERS CNTRL Register (Address X'00EE) T1C3 T1C2 T1C1 T1C0 MSEL Bit 7 The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits: T1C3 Timer T1 mode control bit T1C2 Timer T1 mode control bit ...

  • Page 21

    Timers (Continued) the PMW outputs are useful in controlling motors, triacs, the intensity of displays, and in providing inputs for data acqui- sition and sine wave generators. In this mode, the timer T1 counts down at a fixed rate ...

  • Page 22

    Timers (Continued) 7.2.3 Mode 3. Input Capture Mode The device can precisely measure external frequencies or time external events by placing the timer block, T1, in the input capture mode. In this mode, the reload registers serve as independent ...

  • Page 23

    Timers (Continued) 7.3 TIMER CONTROL FLAGS The control bits and their functions are summarized below. T1C3 Timer mode control T1C2 Timer mode control T1C1 Timer mode control T1C0 Timer Start/Stop control in Modes 1 and 2 (Pro- cessor Independent ...

  • Page 24

    Power Save Modes Today, the proliferation of battery-operated based applica- tions has placed new demands on designers to drive power consumption down. Battery-operated systems are not the only type of applications demanding low power. The power budget constraints are ...

  • Page 25

    Power Save Modes 8.2 IDLE MODE The device is placed in the IDLE mode by writing a “1” to the IDLE flag (G6 data bit). In this mode, all activities, except the associated on-board oscillator circuitry and the IDLE ...

  • Page 26

    Power Save Modes 8.3 MULTI-INPUT WAKEUP The Multi-Input Wakeup feature is used to return (wakeup) the device from either the HALT or IDLE modes. Alternately Multi-Input Wakeup/Interrupt feature may also be used to generate edge selectable ...

  • Page 27

    Interrupts 9.1 INTRODUCTION The device supports eight vectored interrupts. Interrupt sources include Timer 1, Timer T0, Port L Wakeup, Software Trap, MICROWIRE/PLUS, and External Input. All interrupts force a branch to location 00FF Hex in program memory. The VIS ...

  • Page 28

    Interrupts (Continued) 9.2 MASKABLE INTERRUPTS All interrupts other than the Software Trap are maskable. Each maskable interrupt has an associated enable bit and pending flag bit. The pending bit is set to 1 when the interrupt condition occurs. The ...

  • Page 29

    Interrupts (Continued) ample, if the Software Trap routine is located at 0310 Hex, then the vector location 0yFE and -0yFF should contain the data 03 and 10 Hex, respectively. When a Software Trap interrupt occurs and the VIS instruction ...

  • Page 30

    Interrupts (Continued) 9.3.1 VIS Execution When the VIS instruction is executed it activates the arbitra- tion logic. The arbitration logic generates an even number between E0 and FE (E0, E2, E4, E6 etc...) depending on which active interrupt has ...

  • Page 31

    Interrupts (Continued) FIGURE 23. VIS Flowchart 31 DS012838-30 www.national.com ...

  • Page 32

    Interrupts (Continued) Programming Example: External Interrupt PSW =00EF CNTRL =00EE RBIT 0,PORTGC RBIT 0,PORTGD SBIT IEDG, CNTRL SBIT GIE, PSW SBIT EXEN, PSW WAIT: JP WAIT . . . .=0FF VIS . . . .=01FA .ADDRW SERVICE . . ...

  • Page 33

    Interrupts (Continued) 9.4 NON-MASKABLE INTERRUPT 9.4.1 Pending Flag There is a pending flag bit associated with the non-maskable interrupt, called STPND. This pending flag is not memory-mapped and cannot be accessed directly by the software. The pending flag is ...

  • Page 34

    WATCHDOG/Clock Monitor The devices contain a user selectable WATCHDOG and clock monitor. The following section is applicable only if WATCHDOG feature has been selected in the ECON regis- ter. The WATCHDOG is designed to detect the user program getting ...

  • Page 35

    WATCHDOG/Clock Monitor Key Window Data Data Match Match Don’t Care Mismatch Mismatch Don’t Care Don’t Care Don’t Care 10.3 WATCHDOG AND CLOCK MONITOR SUMMARY The following salient points regarding the WATCHDOG and CLOCK MONITOR should be noted: • Both ...

  • Page 36

    MICROWIRE/PLUS MICROWIRE/PLUS is a serial SPI compatible synchronous communications interface. The MICROWIRE/PLUS capabil- ity enables the device to interface with MICROWIRE/PLUS or SPI peripherals (i.e. A/D converters, display drivers, EE- PROMs etc.) and with other microcontrollers which support the ...

  • Page 37

    MICROWIRE/PLUS 11.1.2 MICROWIRE/PLUS Slave Mode Operation In the MICROWIRE/PLUS Slave mode of operation the SK clock is generated by an external source. Setting the MSEL bit in the CNTRL register enables the SO and SK functions onto the G ...

  • Page 38

    MICROWIRE/PLUS FIGURE 27. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High FIGURE 28. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being High www.national.com (Continued) 38 DS012838-35 DS012838-31 ...

  • Page 39

    Memory Map All RAM, ports and registers (except A and PC) are mapped into data memory address space. RAM Select 64 On-Chip RAM Bytes. (COP8SAAx) 128 On-Chip RAM Bytes (COP8SABx/SACx) Reading any undefined memory location in the address range ...

  • Page 40

    Instruction Set 13.1 INTRODUCTION This section defines the instruction set of the COP8SAx Family members. It contains information about the instruc- tion set features, addressing modes and types. 13.2 INSTRUCTION FEATURES The strength of the instruction set is based ...

  • Page 41

    Instruction Set (Continued) Example: Load Accumulator Immediate Reg/Data Contents Memory Before Accumulator XX Hex Immediate Short. This is a special case of an immediate instruction. In the “Load B immediate” instruction, the 4-bit immediate value ...

  • Page 42

    Instruction Set (Continued) Jump Indirect. In this 1-byte instruction, the lower byte of the jump address is obtained from a table stored in program memory, with the Accumulator serving as the low order byte of a pointer into program ...

  • Page 43

    Instruction Set (Continued) 13.4.9 No-Operation Instruction The no-operation instruction does nothing, except to occupy space in the program memory and time in execution. No-Operation (NOP) Note: The VIS is a special case of the Indirect Transfer of Control addressing ...

  • Page 44

    Instruction Set (Continued) 13.6 INSTRUCTION SET SUMMARY ADD A,Meml ADD ADC A,Meml ADD with Carry SUBC A,Meml Subtract with Carry AND A,Meml Logical AND ANDSZ A,Imm Logical AND Immed., Skip if Zero OR A,Meml Logical OR XOR A,Meml Logical ...

  • Page 45

    Instruction Set (Continued) JSRL Addr. Jump SubRoutine Long JSR Addr. Jump SubRoutine JID Jump InDirect RET RETurn from subroutine RETSK RETurn and SKip RETI RETurn from Interrupt INTR Generate an Interrupt NOP No OPeration 13.7 INSTRUCTION EXECUTION TIME Most ...

  • Page 46

    Instruction Set (Continued) Memory Transfer Instructions Register Indirect [ (Note 21) 1 (Note 21) 1 Imm LD B, Imm LD Mem, Imm 2/2 LD Reg, Imm IFEQ MD, Imm > Note 21: = ...

  • Page 47

    Nibble Lower 47 www.national.com ...

  • Page 48

    Mask Options For mask options information on COP8SAx5 devices, please refer to Section 6.4 ECON (CONFIGURATION) REGISTER. 15.0 Development Tools Support 15.1 OVERVIEW National is engaged with an international community of in- dependent 3rd party vendors who provide hardware ...

  • Page 49

    Development Tools Support (Continued) • COP8-UTILS: Free set of COP8 assembly code ex- amples, device drivers, and utilities to speed up code development. • COP8-MLSIM: Free Instruction Level Simulator tool for Windows. For testing and debugging software instruc- tions ...

  • Page 50

    Development Tools Support MetaLink COP8-DM DM5-KCOP8-SA DM Target MHW-CNVxx (xx = 33, 34 Adapters etc.) OTP MHW-COP8-PGMA-DS Programming Adapters MHW-COP8-PGMA-44QFP L MHW-COP8-PGMA-28CSP L COP8-IM IM-COP8-AD-464 (-220) (10 MHz maximum) IM Probe Card PC-COP8SA44PW-AD-10 PC-COP8SA40DW-AD-10 IM Probe Target MHW-SOICxx (xx ...

  • Page 51

    Development Tools Support 15.4 WHERE TO GET TOOLS Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors. Vendor Home Office Aisys U.S.A.: Santa Clara, CA 1-408-327-8820 fax: 1-408-327-8830 ...

  • Page 52

    Physical Dimensions 20-Lead Hermetic Dual-In-Line Package, EPROM (D) www.national.com inches (millimeters) unless otherwise noted Order Number COP8SAC720Q3 NS Package Number D20CQ 52 ...

  • Page 53

    ... Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Order Number COP8SAA716M8 or COP8SAA716M9 Order Number COP8SAA716N8 or COP8SAA716N9 Molded Small Outline Package (WM) NS Package Number M16B Molded Dual-In-Line Package (N) NS Package Number N16A 53 www.national.com ...

  • Page 54

    Physical Dimensions Order Number COP8SAA720M9, COP8SAB720M9, COP8SAC720M9 COP8SAA720M8, COP8SAB720M8 or COP8SAC720M8 Order Number COP8SAA720N9, COP8SAB720N9, COP8SAC720N9, COP8SAA720N8, COP8SAB720N8 or COP8SAC720N8 www.national.com inches (millimeters) unless otherwise noted (Continued) Molded SO Wide Body Package (WM) NS Package Number M20B Molded Dual-In-Line Package ...

  • Page 55

    Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Hermetic Dual-In-Line Package EPROM (D) Order Number COP8SAC728Q3 NS Package Number D28JQ 55 www.national.com ...

  • Page 56

    Physical Dimensions Order Number COP8SAA728M9, COP8SAB728M9, COP8SAC728M9, COP8SAA728M8, COP8SAB728M8 or COP8SAC728M8 Order Number COP8SAA728N9, COP8SAB728N9, COP8SAC728N9, COP8SAA728N8, COP8SAB728N8 or COP8SAC728N8 www.national.com inches (millimeters) unless otherwise noted (Continued) Molded SO Wide Body Package (WM) NS Package Number M28B Molded Dual-In-Line Package ...

  • Page 57

    Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Order Number COP8SAA7SLB9, COP8SAB7SLB9 or COP8SAC7SLB9 28 Lead Chip Scale Package (SLB) NS Package Number SLB28A 57 www.national.com ...

  • Page 58

    Physical Dimensions www.national.com inches (millimeters) unless otherwise noted (Continued) 40-Lead Hermetic DIP EPROM (D) Order Number COP8SAC740Q3 NS Package Number D40KQ Molded Dual-In-Line Package (N) Order Number COP8SAC740N9 or COP8SAC740N8 NS Package Number N40A 58 ...

  • Page 59

    Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 44-Lead EPROM Leaded Chip Carrier (EL) Order Number COP8SAC744Q3 NS Package Number EL44C 59 www.national.com ...

  • Page 60

    ... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...