IC MCU OTP 8BIT 1K 20DIP

COP8SAA720N9

Manufacturer Part NumberCOP8SAA720N9
DescriptionIC MCU OTP 8BIT 1K 20DIP
ManufacturerNational Semiconductor
SeriesCOP8™ 8SA
COP8SAA720N9 datasheet
 


Specifications of COP8SAA720N9

Core ProcessorCOP8Core Size8-Bit
Speed10MHzConnectivityMicrowire/Plus (SPI)
PeripheralsPOR, PWM, WDTNumber Of I /o16
Program Memory Size1KB (1K x 8)Program Memory TypeOTP
Ram Size64 x 8Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 V
Oscillator TypeInternalOperating Temperature0°C ~ 70°C
Package / Case20-DIP (0.300", 7.62mm)Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Eeprom Size-Data Converters-
Other names*COP8SAA720N9
COP8SAA720N9B
COP8SAA720NB
  
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6.0 Functional Description
6.7 RESET
The device is initialized when the RESET pin is pulled low or
the On-chip Power-On Reset is enabled.
FIGURE 8. Reset Logic
The following occurs upon initialization:
Port L: TRISTATE
Port C: TRISTATE
Port G: TRISTATE
Port F: TRISTATE
Port D: HIGH
PC: CLEARED to 0000
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR: UNAFFECTED after RESET with power already
applied
RANDOM after RESET at power-on
T1CNTRL: CLEARED
Accumulator, Timer 1:
RANDOM after RESET with crystal clock option
(power already applied)
UNAFFECTED after RESET with R/C clock option
(power already applied)
RANDOM after RESET at power-on
WKEN, WKEDG: CLEARED
WKPND: RANDOM
SP (Stack Pointer):
Initialized to RAM address 02F Hex (devices with
64 bytes of RAM), or initialized to
RAM address 06F Hex (devices with
128 bytes of RAM).
B and X Pointers:
UNAFFECTED after RESET with power
already applied
RANDOM after RESET at power-on
RAM:
UNAFFECTED after RESET with power already
applied
RANDOM after RESET at power-on
WATCHDOG (if enabled):
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are
inhibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t
clock cycles. The Clock Monitor bit
C
being initialized high will cause a Clock Monitor error follow-
ing reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
(Continued)
will cause an active low error output on pin G1. This error
output will continue until 16 t
the clock frequency reaching the minimum specified value,
at which time the G1 output will go high.
6.7.1 External Reset
The RESET input when pulled low initializes the device. The
RESET pin must be held low for a minimum of one instruc-
tion cycle to guarantee a valid reset. During Power-Up ini-
tialization, the user must ensure that the RESET pin is held
low until the device is within the specified V
R/C circuit on the RESET pin with a delay 5 times (5x)
greater than the power supply rise time or 15 µs whichever is
DS012838-13
greater, is recommended. Reset should also be wide enough
to ensure crystal start-up upon Power-Up.
RESET may also be used to cause an exit from the HALT
mode.
A recommended reset circuit for this deviced is shown in
Figure 9 .
>
RC
5x power supply rise time or 15 µs, whichever is greater.
FIGURE 9. Reset Circuit Using External Reset
6.7.2 On-Chip Power-On Reset
The on-chip reset circuit is selected by a bit in the ECON
register. When enabled, the device generates an internal
reset as V
rises to a voltage level above 2.0V. The on-chip
CC
reset circuitry is able to detect both fast and slow rise times
on V
(V
rise time between 10 ns and 50 ms).
CC
CC
Under no circumstances should the RESET pin be allowed
to float. If the on-chip Power-On Reset feature is being used,
RESET pin should be connected directly to V
of the power-on reset detector will always preset the Idle
timer to 0FFF(4096 t
generated.
If the Power-On Reset feature is enabled, the internal reset
will not be turned off until the Idle timer underflows. The
internal reset will perform the same functions as external
reset. The user is responsible for ensuring that V
minimum level for the operating frequency within the 4096
t
. After the underflow, the logic is designed such that no
C
additional internal resets occur as long as V
above 2.0V.
Note: While the POR feature of the COP8SAx was never intended to function
as a brownout detector, there are certain constraints of this block that
the system designer must address to properly recover from a brownout
condition. This is true regardless of whether the internal POR or the
external reset feature is used.
A brownout condition is reached when V
the minimum operating conditions of the device. The minimum guar-
anteed operating conditions are defined as V
@
V
= 2.7V
CC
is stopped) operation.
When using either the external reset or the POR feature to recover
from a brownout condition, V
external reset must be applied whenever it goes below the minimum
operating conditions as stated above.
17
–32 t
clock cycles following
C
C
voltage. An
CC
DS012838-14
. The output
CC
). At this time, the internal reset will be
C
is at the
CC
remains
CC
of the device goes below
CC
= 4.5V
@
10 MHz CKI,
CC
4 MHz, or V
= 2.0V during HALT mode (or when CKI
CC
must be lowered to 0.25V or an
CC
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