IC MCU OTP 8BIT 1K 20DIP

COP8SAA720N9

Manufacturer Part NumberCOP8SAA720N9
DescriptionIC MCU OTP 8BIT 1K 20DIP
ManufacturerNational Semiconductor
SeriesCOP8™ 8SA
COP8SAA720N9 datasheet
 


Specifications of COP8SAA720N9

Core ProcessorCOP8Core Size8-Bit
Speed10MHzConnectivityMicrowire/Plus (SPI)
PeripheralsPOR, PWM, WDTNumber Of I /o16
Program Memory Size1KB (1K x 8)Program Memory TypeOTP
Ram Size64 x 8Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 V
Oscillator TypeInternalOperating Temperature0°C ~ 70°C
Package / Case20-DIP (0.300", 7.62mm)Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Eeprom Size-Data Converters-
Other names*COP8SAA720N9
COP8SAA720N9B
COP8SAA720NB
  
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10.0 WATCHDOG/Clock Monitor
The devices contain a user selectable WATCHDOG and
clock monitor. The following section is applicable only if
WATCHDOG feature has been selected in the ECON regis-
ter. The WATCHDOG is designed to detect the user program
getting stuck in infinite loops resulting in loss of program
control or “runaway” programs.
The WATCHDOG logic contains two separate service win-
dows. While the user programmable upper window selects
the WATCHDOG service time, the lower window provides
protection against an infinite program loop that contains the
WATCHDOG service instruction.
The COP8SAx devices provide the added feature of a soft-
ware trap that provides protection against stack overpops
and addressing locations outside valid user program space.
The Clock Monitor is used to detect the absence of a clock or
a very slow clock below a specified rate on the CKI pin.
The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific
value to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is com-
posed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table 6 shows the WDSVR register.
TABLE 6. WATCHDOG Service Register (WDSVR)
Window
Key Data
Select
X
X
0
1
1
The lower limit of the service window is fixed at 256 instruc-
tion cycles. Bits 7 and 6 of the WDSVR register allow the
user to pick an upper limit of the service window.
Table 7 shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flex-
ibility in choosing the WATCHDOG service window prevents
any undue burden on the user software.
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the
5-bit Key Data field. The key data is fixed at 01100. Bit 0 of
the WDSVR Register is the Clock Monitor Select bit.
TABLE 7. WATCHDOG Service Window Select
WDSVR WDSVR
Clock
Bit 7
Bit 6
Monitor
(Lower-Upper Limits)
0
0
x
2048–8k t
0
1
x
2048–16k t
1
0
x
2048–32k t
1
1
x
2048–64k t
x
x
0
Clock Monitor Disabled
x
x
1
Clock Monitor Enabled
10.1 CLOCK MONITOR
The Clock Monitor aboard the device can be selected or
deselected under program control. The Clock Monitor is
guaranteed not to reject the clock if the instruction cycle
clock (1/t
) is greater or equal to 10 kHz. This equates to a
C
clock input rate on CKI of greater or equal to 100 kHz.
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10.2 WATCHDOG/CLOCK MONITOR OPERATION
The WATCHDOG is enabled by bit 2 of the ECON register.
When this ECON bit is 0, the WATCHDOG is enabled and
pin G1 becomes the WATCHDOG output with a weak pullup.
The WATCHDOG and Clock Monitor are disabled during
reset. The device comes out of reset with the WATCHDOG
armed, the WATCHDOG Window Select bits (bits 6, 7 of the
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the
WDSVR Register) enabled. Thus, a Clock Monitor error will
occur after coming out of reset, if the instruction cycle clock
frequency has not reached a minimum specified value, in-
cluding the case where the oscillator fails to start.
The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, select
the WATCHDOG service window and match the WATCH-
DOG key data. Subsequent writes to the WDSVR register
will compare the value being written by the user to the
WATCHDOG service window value and the key data (bits 7
through 1) in the WDSVR Register. Table 8 shows the se-
quence of events that can occur.
The user must service the WATCHDOG at least once before
the upper limit of the service window expires. The WATCH-
DOG may not be serviced more than once in every lower
limit of the service window. The user may service the
WATCHDOG as many times as wished in the time period
between the lower and upper limits of the service window.
The first write to the WDSVR Register is also counted as a
Clock
WATCHDOG service.
Monitor
The WATCHDOG has an output pin associated with it. This
0
0
Y
is the WDOUT pin, on pin 1 of the port G. WDOUT is active
low and must be externally connected to the RESET pin or to
some other external logic which handles WATCHDOG event.
The WDOUT pin has a weak pullup in the inactive state. This
pull-up is sufficient to serve as the connection to V
systems which use the internal Power On Reset. Upon
triggering the WATCHDOG, the logic will pull the WDOUT
(G1) pin low for an additional 16 t
signal level on WDOUT pin goes below the lower Schmitt
trigger threshold. After this delay, the device will stop forcing
the WDOUT output low. The WATCHDOG service window
will restart when the WDOUT pin goes high.
A WATCHDOG service while the WDOUT signal is active will
be ignored. The state of the WDOUT pin is not guaranteed
on reset, but if it powers up low then the WATCHDOG will
Service Window
time out and WDOUT will go high.
The Clock Monitor forces the G1 pin low upon detecting a
Cycles
clock frequency error. The Clock Monitor error will continue
C
until the clock frequency has reached the minimum specified
Cycles
C
value, after which the G1 output will go high following 16
Cycles
C
t
–32 t
C
C
Cycles
tinual Clock Monitor error if the oscillator fails to start, or fails
C
to reach the minimum specified frequency. The specification
for the Clock Monitor is as follows:
>
1/t
C
<
1/t
C
34
–32 t
cycles after the
C
C
clock cycles. The Clock Monitor generates a con-
10 kHz — No clock rejection.
10 Hz — Guaranteed clock rejection.
for
CC