IC MCU OTP 8BIT 1K 20DIP

COP8SAA720N9

Manufacturer Part NumberCOP8SAA720N9
DescriptionIC MCU OTP 8BIT 1K 20DIP
ManufacturerNational Semiconductor
SeriesCOP8™ 8SA
COP8SAA720N9 datasheet
 


Specifications of COP8SAA720N9

Core ProcessorCOP8Core Size8-Bit
Speed10MHzConnectivityMicrowire/Plus (SPI)
PeripheralsPOR, PWM, WDTNumber Of I /o16
Program Memory Size1KB (1K x 8)Program Memory TypeOTP
Ram Size64 x 8Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 V
Oscillator TypeInternalOperating Temperature0°C ~ 70°C
Package / Case20-DIP (0.300", 7.62mm)Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Eeprom Size-Data Converters-
Other names*COP8SAA720N9
COP8SAA720N9B
COP8SAA720NB
  
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Page 36/60

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11.0 MICROWIRE/PLUS
MICROWIRE/PLUS is a serial SPI compatible synchronous
communications interface. The MICROWIRE/PLUS capabil-
ity enables the device to interface with MICROWIRE/PLUS
or SPI peripherals (i.e. A/D converters, display drivers, EE-
PROMs etc.) and with other microcontrollers which support
the MICROWIRE/PLUS or SPI interface. It consists of an
8-bit serial shift register (SIO) with serial data input (SI),
serial data output (SO) and serial shift clock (SK). Figure 24
shows a block diagram of the MICROWIRE/PLUS logic.
The shift clock can be selected from either an internal source
or an external source. Operating the MICROWIRE/PLUS
arrangement with the internal clock source is called the
Master mode of operation. Similarly, operating the
MICROWIRE/PLUS arrangement with an external shift clock
is called the Slave mode of operation.
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. In the
master mode, the SK clock rate is selected by the two bits,
SL0 and SL1, in the CNTRL register. Table 9 details the
different clock rates that may be selected.
TABLE 9. MICROWIRE/PLUS
Master Mode Clock Select
SL1
SL0
0
0
0
1
1
x
Where t
is the instruction cycle clock
C
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11.1 MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the
MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 24 shows how
two microcontroller devices and several peripherals may be
interconnected using the MICROWIRE/PLUS arrangements.
The SIO register should only be loaded when the SK clock is
in the idle phase. Loading the SIO register while the SK clock
is in the active phase, will result in undefined data in the SIO
register.
Setting the BUSY flag when the input SK clock is in the
active phase while in the MICROWIRE/PLUS is in the slave
mode may cause the current SK clock for the SIO shift
register to be narrow. For safety, the BUSY flag should only
be set when the input SK clock is in the idle phase.
11.1.1 MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE
Master always initiates all data exchanges. The MSEL bit in
the CNTRL register must be set to enable the SO and SK
functions onto the G Port. The SO and SK pins must also be
SK Period
selected as outputs by setting appropriate bits in the Port G
2 x t
C
configuration register. In the slave mode, the shift clock
4 x t
stops after 8 clock pulses. Table 10 summarizes the bit
C
8 x t
settings required for Master mode of operation.
C
FIGURE 24. MICROWIRE/PLUS Application
36
WARNING
DS012838-32