IC MCU OTP 8BIT 1K 20DIP

COP8SAA720N9

Manufacturer Part NumberCOP8SAA720N9
DescriptionIC MCU OTP 8BIT 1K 20DIP
ManufacturerNational Semiconductor
SeriesCOP8™ 8SA
COP8SAA720N9 datasheet
 


Specifications of COP8SAA720N9

Core ProcessorCOP8Core Size8-Bit
Speed10MHzConnectivityMicrowire/Plus (SPI)
PeripheralsPOR, PWM, WDTNumber Of I /o16
Program Memory Size1KB (1K x 8)Program Memory TypeOTP
Ram Size64 x 8Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 V
Oscillator TypeInternalOperating Temperature0°C ~ 70°C
Package / Case20-DIP (0.300", 7.62mm)Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Eeprom Size-Data Converters-
Other names*COP8SAA720N9
COP8SAA720N9B
COP8SAA720NB
  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Page 31
32
Page 32
33
Page 33
34
Page 34
35
Page 35
36
Page 36
37
Page 37
38
Page 38
39
Page 39
40
Page 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Page 37/60

Download datasheet (777Kb)Embed
PrevNext
11.0 MICROWIRE/PLUS
11.1.2 MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bits in the Port G configuration
register. Table 10 summarizes the settings required to enter
the Slave mode of operation.
This table assumes that the control flag MSEL is set.
TABLE 10. MICROWIRE/PLUS Mode Settings
G4 (SO)
G5 (SK)
G4
G5
Config. Bit
Config. Bit
Fun.
Fun.
1
1
SO
Int.
SK
0
1
TRI-
Int.
STATE
SK
1
0
SO
Ext.
SK
0
0
TRI-
Ext.
STATE
SK
TABLE 11. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase
Port G
SK Phase
G6 (SKSEL)
Config. Bit
Normal
0
Alternate
1
Alternate
0
Normal
1
FIGURE 25. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being Low
FIGURE 26. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being Low
The user must set the BUSY flag immediately upon entering
(Continued)
the Slave mode. This ensures that all data bits sent by the
Master is shifted properly. After eight clock pulses the BUSY
flag is clear, the shift clock is stopped, and the sequence
may be repeated.
10.1.3 Alternate SK Phase Operation
and SK Idle Polarity
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register. In
both the modes the SK idle polarity can be either high or low.
The polarity is selected by bit 5 of Port G data register. In the
normal mode data is shifted in on the rising edge of the SK
clock and the data is shifted out on the falling edge of the SK
clock. The SIO register is shifted on each falling edge of the
SK clock. In the alternate SK phase operation, data is shifted
Operation
in on the falling edge of the SK clock and shifted out on the
rising edge of the SK clock. Bit 6 of Port G configuration
MICROWIRE/PLUS
register selects the SK edge.
Master
A control flag, SKSEL, allows either the normal SK clock or
MICROWIRE/PLUS
the alternate SK clock to be selected. Resetting SKSEL
Master
causes the MICROWIRE/PLUS logic to be clocked from the
MICROWIRE/PLUS
normal SK signal. Setting the SKSEL flag selects the alter-
Slave
nate SK clock. The SKSEL is mapped into the G6 configu-
MICROWIRE/PLUS
ration bit. The SKSEL flag will power up in the reset condi-
Slave
tion, selecting the normal SK signal.
G5
SO Clocked Out On:
Data Bit
0
SK Falling Edge
0
SK Rising Edge
1
SK Rising Edge
1
SK Falling Edge
37
SK Idle
SI Sampled On:
Phase
SK Rising Edge
Low
SK Falling Edge
Low
SK Falling Edge
High
SK Rising Edge
High
DS012838-33
DS012838-34
www.national.com