COP8SAA728N9 National Semiconductor, COP8SAA728N9 Datasheet - Page 15

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COP8SAA728N9

Manufacturer Part Number
COP8SAA728N9
Description
IC MCU OTP 8BIT 1K 28DIP
Manufacturer
National Semiconductor
Series
COP8™ 8SAr
Datasheet

Specifications of COP8SAA728N9

Core Processor
COP8
Core Size
8-Bit
Speed
10MHz
Connectivity
Microwire/Plus (SPI)
Peripherals
POR, PWM, WDT
Number Of I /o
24
Program Memory Size
1KB (1K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
*COP8SAA728N9
COP8SAA728N9B
5.0 Pin Descriptions
(Continued)
FIGURE 5. I/O Port Configurations
FIGURE 6. I/O Port Configurations — Output Mode
FIGURE 7. I/O Port Configurations — Input Mode
Port D is an 8-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs
(except D2) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At RESET, the
external loads on this pin must ensure that the output voltages stay
above 0.7 V
to prevent the chip from entering special modes. Also
CC
keep the external loading on D2 to less than 1000 pF.
6.0 Functional Description
The architecture of the device is a modified Harvard archi-
tecture. With the Harvard architecture, the program memory
EPROM is separated from the data store memory (RAM).
Both EPROM and RAM have their own separate addressing
space with separate address buses. The architecture,
though based on the Harvard architecture, permits transfer
of data from EPROM to RAM.
6.1 CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (t
There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
DS012838-10
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). With reset the SP is initialized to
RAM address 02F Hex (devices with 64 bytes of RAM), or
initialized to RAM address 06F Hex (devices with 128 bytes
of RAM).
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).
6.2 PROGRAM MEMORY
The program memory consists of 1024, 2048, or 4096 bytes
of EPROM or ROM. Table 1 shows the program memory
DS012838-12
sizes for the different devices. These bytes may hold pro-
gram instructions or constant data (data tables for the LAID
instruction, jump vectors for the JID instruction, and interrupt
vectors for the VIS instruction). The program memory is
addressed by the 15-bit program counter (PC). All interrupts
in the device vector to program memory location 0FF Hex.
The program memory reads 00 Hex in the erased state.
6.3 DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X and SP pointers.
The data memory consists of 64 or 128 bytes of RAM. Table
1 shows the data memory sizes for the different devices.
Fifteen bytes of RAM are mapped as “registers” at ad-
DS012838-11
dresses 0F0 to 0FE Hex. These registers can be loaded
immediately, and also decremented and tested with the
DRSZ (decrement register and skip if zero) instruction. The
memory pointer registers X, SP and B are memory mapped
into this space at address locations 0FC to 0FE Hex respec-
tively, with the other registers (except 0FF) being available
for general usage. Address location 0FF is reserved for
future RAM expansion. If compatibility with future devices
(with more RAM) is not desired, this location can be used as
a general purpose RAM location.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
15
) cycle time.
C
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