COP8SAA728N9 National Semiconductor, COP8SAA728N9 Datasheet - Page 37

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COP8SAA728N9

Manufacturer Part Number
COP8SAA728N9
Description
IC MCU OTP 8BIT 1K 28DIP
Manufacturer
National Semiconductor
Series
COP8™ 8SAr
Datasheet

Specifications of COP8SAA728N9

Core Processor
COP8
Core Size
8-Bit
Speed
10MHz
Connectivity
Microwire/Plus (SPI)
Peripherals
POR, PWM, WDT
Number Of I /o
24
Program Memory Size
1KB (1K x 8)
Program Memory Type
OTP
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
*COP8SAA728N9
COP8SAA728N9B
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11.0 MICROWIRE/PLUS
11.1.2 MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bits in the Port G configuration
register. Table 10 summarizes the settings required to enter
the Slave mode of operation.
This table assumes that the control flag MSEL is set.
SK Phase
Alternate
Alternate
Config. Bit
Normal
Normal
G4 (SO)
TABLE 10. MICROWIRE/PLUS Mode Settings
1
0
1
0
FIGURE 26. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being Low
FIGURE 25. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being Low
Config. Bit
G5 (SK)
1
1
0
0
G6 (SKSEL)
Config. Bit
TABLE 11. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase
0
1
0
1
STATE
STATE
Fun.
TRI-
TRI-
SO
SO
G4
Port G
Fun.
Ext.
Ext.
G5
Int.
SK
Int.
SK
SK
SK
(Continued)
MICROWIRE/PLUS
Master
MICROWIRE/PLUS
Master
MICROWIRE/PLUS
Slave
MICROWIRE/PLUS
Slave
Data Bit
Operation
G5
0
0
1
1
37
SO Clocked Out On:
SK Falling Edge
SK Falling Edge
SK Rising Edge
SK Rising Edge
The user must set the BUSY flag immediately upon entering
the Slave mode. This ensures that all data bits sent by the
Master is shifted properly. After eight clock pulses the BUSY
flag is clear, the shift clock is stopped, and the sequence
may be repeated.
10.1.3 Alternate SK Phase Operation
and SK Idle Polarity
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register. In
both the modes the SK idle polarity can be either high or low.
The polarity is selected by bit 5 of Port G data register. In the
normal mode data is shifted in on the rising edge of the SK
clock and the data is shifted out on the falling edge of the SK
clock. The SIO register is shifted on each falling edge of the
SK clock. In the alternate SK phase operation, data is shifted
in on the falling edge of the SK clock and shifted out on the
rising edge of the SK clock. Bit 6 of Port G configuration
register selects the SK edge.
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alter-
nate SK clock. The SKSEL is mapped into the G6 configu-
ration bit. The SKSEL flag will power up in the reset condi-
tion, selecting the normal SK signal.
SI Sampled On:
SK Falling Edge
SK Falling Edge
SK Rising Edge
SK Rising Edge
DS012838-33
DS012838-34
www.national.com
SK Idle
Phase
High
High
Low
Low

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