MC68HC705C8ACFN Freescale Semiconductor, MC68HC705C8ACFN Datasheet - Page 95

IC MCU 4MHZ 8K OTP 44-PLCC

MC68HC705C8ACFN

Manufacturer Part Number
MC68HC705C8ACFN
Description
IC MCU 4MHZ 8K OTP 44-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705C8ACFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
304 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-

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MC68HC705C8A — Rev. 3
MOTOROLA
ICIE — Input Capture Interrupt Enable Bit
OCIE — Output Compare Interrupt Enable Bit
TOIE — Timer Overflow Interrupt Enable Bit
IEDG — Input Edge Bit
OLVL — Output Level Bit
Bits 4–2 — Not used; these bits always read 0
This read/write bit enables interrupts caused by an active signal on
the TCAP pin. Reset clears the ICIE bit.
This read/write bit enables interrupts caused by an active signal on
the TCMP pin. Reset clears the OCIE bit.
This read/write bit enables interrupts caused by a timer overflow.
Reset clears the TOIE bit.
The state of this read/write bit determines whether a positive or
negative transition on the TCAP pin triggers a transfer of the contents
of the timer register to the input capture registers. Reset has no effect
on the IEDG bit.
The state of this read/write bit determines whether a logic 1 or a
logic 0 appears on the TCMP pin when a successful output compare
occurs. Reset clears the OLVL bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
1 = Positive edge (low-to-high transition) triggers input capture
0 = Negative edge (high-to-low transition) triggers input capture
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
Go to: www.freescale.com
Capture/Compare Timer
Capture/Compare Timer
Timer I/O Registers
Technical Data
95

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