MC68HC705C8ACP Freescale Semiconductor, MC68HC705C8ACP Datasheet - Page 142

IC MCU 4MHZ 8K OTP 40-DIP

MC68HC705C8ACP

Manufacturer Part Number
MC68HC705C8ACP
Description
IC MCU 4MHZ 8K OTP 40-DIP
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705C8ACP

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
304 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-

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Manufacturer
Quantity
Price
Part Number:
MC68HC705C8ACP
Manufacturer:
MOTOROLA
Quantity:
13
Part Number:
MC68HC705C8ACP
Manufacturer:
FREESCALE
Quantity:
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ON
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Serial Peripheral Interface (SPI)
11.4 Operation
Technical Data
142
$000A
$000B
$000C
Addr.
SPI Control Register
SPI Status Register
SPI Data Register
Register Name
See page 149.
See page 151.
See page 149.
(SPCR)
(SPDR)
(SPSR)
The master/slave SPI allows full-duplex, synchronous, serial
communication between the microcontroller unit (MCU) and peripheral
devices, including other MCUs. As the 8-bit shift register of a master SPI
transmits each byte to another device, a byte from the receiving device
enters the master SPI shift register. A clock signal from the master SPI
synchronizes data transmission.
Only a master SPI can initiate transmissions. Software begins the
transmission from a master SPI by writing to the SPI data register
(SPDR). The SPDR does not buffer data being transmitted from the SPI.
Data written to the SPDR goes directly into the shift register and begins
the transmission immediately under the control of the serial clock. The
transmission ends after eight cycles of the serial clock when the SPI flag
(SPIF) becomes set. At the same time that SPIF becomes set, the data
shifted into the master SPI from the receiving device transfers to the
SPDR. The SPDR buffers data being received by the SPI. Before the
master SPI sends the next byte, software must clear the SPIF bit by
reading the SPSR and then accessing the SPDR.
Freescale Semiconductor, Inc.
Figure 11-2. SPI I/O Register Summary
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
For More Information On This Product,
Serial Peripheral Interface (SPI)
SPIE
SPIF
Bit 7
Bit 7
0
0
Go to: www.freescale.com
= Unimplemented
WCOL
SPE
Bit 6
6
0
0
Bit 5
5
U = Unaffected
MODF
MSTR
Unaffected by reset
Bit 4
4
0
0
CPOL
Bit 3
U
3
MC68HC705C8A — Rev. 3
CPHA
BIt 2
U
2
SPR1
Bit 1
U
1
MOTOROLA
SPR0
Bit 0
Bit 0
U

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