MC68HC705C8ACP Freescale Semiconductor, MC68HC705C8ACP Datasheet - Page 156

IC MCU 4MHZ 8K OTP 40-DIP

MC68HC705C8ACP

Manufacturer Part Number
MC68HC705C8ACP
Description
IC MCU 4MHZ 8K OTP 40-DIP
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705C8ACP

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
24
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
304 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC705C8ACP
Manufacturer:
MOTOROLA
Quantity:
13
Part Number:
MC68HC705C8ACP
Manufacturer:
FREESCALE
Quantity:
1 487
Part Number:
MC68HC705C8ACPE
Manufacturer:
ON
Quantity:
1 000
Instruction Set
12.3.5 Indexed, No Offset
12.3.6 Indexed, 8-Bit Offset
12.3.7 Indexed, 16-Bit Offset
Technical Data
156
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Instruction Set
MC68HC705C8A — Rev. 3
MOTOROLA

Related parts for MC68HC705C8ACP