IC MCU 4MHZ 1.2K OTP 20-SOIC

MC68HC705J1ACDW

Manufacturer Part NumberMC68HC705J1ACDW
DescriptionIC MCU 4MHZ 1.2K OTP 20-SOIC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705J1ACDW datasheet
 

Specifications of MC68HC705J1ACDW

Core ProcessorHC05Core Size8-Bit
Speed4MHzPeripheralsPOR, WDT
Number Of I /o14Program Memory Size1.2KB (1.2K x 8)
Program Memory TypeOTPRam Size64 x 8
Voltage - Supply (vcc/vdd)3 V ~ 5.5 VOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case20-SOIC (7.5mm Width)
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantEeprom Size-
Data Converters-Connectivity-
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Freescale Semiconductor, Inc.
External Interrupt Module (IRQ)
8.3.1 IRQ/V
Pin
PP
An interrupt signal on the IRQ/V
request. The LEVEL bit in the mask option register provides negative
edge-sensitive triggering or both negative edge-sensitive and low
level-sensitive triggering for the interrupt function.
If edge- and level-sensitive triggering is selected, a falling edge or a low
level on the IRQ/V
level-sensitive triggering allows the use of multiple wired-OR external
interrupt sources. An external interrupt request is latched as long as any
source is holding the IRQ/V
If level-sensitive triggering is selected, the IRQ/V
external resistor to V
used, it must be tied to the V
If edge-sensitive-only triggering is selected, a falling edge on the
IRQ/V
interrupt request can be latched only after the voltage level on the
IRQ/V
The IRQ/V
to improve noise immunity. The voltage on this pin can affect the mode
of operation and should not exceed V
8.3.2 Optional External Interrupts
The inputs for the lower four bits of port A (PA0–PA3) can be connected
to the IRQ pin input of the CPU if enabled by the PIRQ bit in the mask
option register. This capability allows keyboard scan applications where
the transitions or levels on the I/O pins will behave the same as the
IRQ/V
active state of the IRQ/V
The PA0–PA3 pins are selected as a group to function as IRQ interrupts
and are enabled by the IRQE bit in the IRQ status and control register.
The PA0–PA3 pins can be positive-edge triggered only or positive-edge
and high-level triggered.
Technical Data
PP
pin latches an external interrupt request. Edge- and
PP
pin low.
PP
for wired-OR operation. If the IRQ/V
DD
supply.
DD
pin latches an external interrupt request. A subsequent external
PP
pin returns to logic 1 and then falls again to logic 0.
PP
pin contains an internal Schmitt trigger as part of its input
PP
pin except for the inverted phase (logic 1, rising edge). The
PP
pin is a logic 0 (falling edge).
PP
External Interrupt Module (IRQ)
For More Information On This Product,
Go to: www.freescale.com
pin latches an external interrupt
input requires an
PP
pin is not
PP
.
DD
MC68HC705J1A — Rev. 4.0