MC68HC705KJ1CDW Freescale Semiconductor, MC68HC705KJ1CDW Datasheet - Page 51

• Manufacturer Part Number: MC68HC705KJ1CDW
• Description: IC MCU 4MHZ 1.2K OTP 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705KJ1CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 10
• Program Memory Size: 1.2KB (1.2K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Chapter 5
External Interrupt Module (IRQ)
5.1 Introduction
The external interrupt (IRQ) module provides asynchronous external interrupts to the CPU. The following
sources can generate external interrupts:
5.2 Features
The external interrupt module (IRQ) includes these features:
5.3 Operation
The interrupt request/programming voltage pin (IRQ/V
external interrupts. The PIRQ bit in the mask option register (MOR) enables PA0–PA3 as IRQ interrupt
sources, which are combined into a single OR’ing function to be latched by the IRQ latch.
shows the structure of the IRQ module.
After completing its current instruction, the CPU tests the IRQ latch. If the IRQ latch is set, the CPU then
tests the I bit in the condition code register and the IRQE bit in the IRQ status and control register. If the
I bit is clear and the IRQE bit is set, the CPU then begins the interrupt sequence. This interrupt is serviced
by the interrupt service routine located at $07FA and $07FB.
The CPU clears the IRQ latch while it fetches the interrupt vector, so that another external interrupt
request can be latched during the interrupt service routine. As soon as the I bit is cleared during the return
from interrupt, the CPU can recognize the new interrupt request.
caused by an interrupt.
5.3.1 IRQ/V
An interrupt signal on the IRQ/V
option register provides negative edge-sensitive triggering or both negative edge-sensitive and low
level-sensitive triggering for the interrupt function.
If edge- and level-sensitive triggering is selected, a falling edge or a low level on the IRQ/V
an external interrupt request. Edge- and level-sensitive triggering allows the use of multiple wired-OR
external interrupt sources. An external interrupt request is latched as long as any source is holding the
IRQ/V
If level-sensitive triggering is selected, the IRQ/V
operation. If the IRQ/V
Freescale Semiconductor
•
•
•
•
•
PP
IRQ/V
PA0–PA3 pins
Dedicated external interrupt pin (IRQ/V
Selectable interrupt on four input/output (I/O) pins (PA0–PA3)
Programmable edge-only or edge- and level-interrupt sensitivity
pin low.
PP
PP
pin
Pin
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
PP
pin is not used, it must be tied to the V
PP
pin latches an external interrupt request. The LEVEL bit in the mask
PP
PP
)
input requires an external resistor to V
PP
) and port A pins 0–3 (PA0–PA3) provide
Figure 5-3
DD
supply.
shows the sequence of events
DD
PP
Figure 5-1
for wired-OR
pin latches
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