MC68HC705KJ1CDW Freescale Semiconductor, MC68HC705KJ1CDW Datasheet - Page 57

• Manufacturer Part Number: MC68HC705KJ1CDW
• Description: IC MCU 4MHZ 1.2K OTP 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705KJ1CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 10
• Program Memory Size: 1.2KB (1.2K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Chapter 6
Low-Power Modes
6.1 Introduction
The MCU can enter the following low-power standby modes:
6.2 Exiting Stop and Wait Modes
The following events bring the MCU out of stop mode and load the program counter with the reset vector
or with an interrupt vector:
Exiting Stop Mode
Exiting Wait Mode
Freescale Semiconductor
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Stop mode — The STOP instruction puts the MCU in its lowest power-consumption mode.
Wait mode — The WAIT instruction puts the MCU in an intermediate power-consumption mode.
Halt mode — Halt mode is identical to wait mode, except that an oscillator stabilization delay of 1
to 4064 internal clock cycles occurs when the MCU exits halt mode. The stop-to-wait conversion
bit, SWAIT, in the mask option register, enables halt mode.
Enabling halt mode prevents the computer operating properly (COP) watchdog from being
inadvertently turned off by a STOP instruction.
Data-retention mode — In data-retention mode, the MCU retains RAM contents and CPU register
contents at V
in a low power-consumption state during which it retains data, but the CPU cannot execute
instructions.
External reset — A logic 0 on the RESET pin resets the MCU, starts the CPU clock, and loads the
program counter with the contents of locations $07FE and $07FF.
External interrupt — A high-to-low transition on the IRQ/V
enabled port A external interrupt pin starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
External reset — A logic 0 on the RESET pin resets the MCU, starts the CPU clock, and loads the
program counter with the contents of locations $07FE and $07FF.
External interrupt — A high-to-low transition on the IRQ/V
enabled port A external interrupt pin starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
COP watchdog reset — A timeout of the COP watchdog resets the MCU, starts the CPU clock, and
loads the program counter with the contents of locations $07FE and $07FF. Software can enable
timer interrupts so that the MCU periodically can exit wait mode to reset the COP watchdog.
Timer interrupt — Real-time interrupt requests and timer overflow interrupt requests start the MCU
clock and load the program counter with the contents of locations $07F8 and $07F9.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
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voltages as low as 2.0 Vdc. The data-retention feature allows the MCU to remain
PP
PP
pin or a low-to-high transition on an
pin or a low-to-high transition on an
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