MC68HC705KJ1CDW Freescale Semiconductor, MC68HC705KJ1CDW Datasheet - Page 63

• Manufacturer Part Number: MC68HC705KJ1CDW
• Description: IC MCU 4MHZ 1.2K OTP 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705KJ1CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 10
• Program Memory Size: 1.2KB (1.2K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Chapter 7
Parallel I/O Ports (PORTS)
7.1 Introduction
Ten bidirectional pins form one 8-bit input/output (I/O) port and one 2-bit I/O port. All the bidirectional port
pins are programmable as inputs or outputs.
Freescale Semiconductor
$0000
$0001
$0004
$0005
$0010
$0011
Addr.
Note:
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are available for read/write but are not
available externally. Configuring them as inputs will ensure that the pulldown devices are enabled, thus properly termi-
nating them.
Port A Data Register (POR-
Data Direction Register A
Data Direction Register B
Port A Pulldown Register
Port B Pulldown Register
Register Name:
Port B Data Register
Connect any unused I/O pins to an appropriate logic level, either V
V
termination reduces excess current consumption and the possibility of
electrostatic damage.
SS.
See page 64.
See page 66.
See page 64.
See page 67.
See page 65.
See page 68.
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
Although the I/O ports do not require termination for proper operation,
(PORTB)
(DDRA)
(DDRB)
(PDRA)
(PDRB)
TA)
Figure 7-1. Parallel I/O Port Register Summary
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
DDRA7
PDIA7
Bit 7
PA7
0
0
0
0
0
= Unimplemented
DDRA6
PDIA6
PA6
6
0
0
0
0
0
NOTE
DDRA5
PDIA5
PA5
5
0
0
0
0
See Note
See Note
See Note
DDRA4
Unaffected by reset
Unaffected by reset
PDIA4
PA4
4
0
0
0
0
DDRA3
DDRB3
PDIA3
PDIB3
PA3
PB3
3
0
0
0
0
DDRA2
DDRB2
PDIA2
PDIB2
PA2
PB2
2
0
0
0
0
DD
or
DDRA1
PDIA1
PA1
1
0
0
0
0
See Note
See Note
See Note
DDRA0
PDIA0
Bit 0
PA0
0
0
0
0
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