MC68HC705B16CFN

Manufacturer Part NumberMC68HC705B16CFN
DescriptionIC MCU 2.1MHZ 15K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705B16CFN datasheet
 


Specifications of MC68HC705B16CFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI
PeripheralsPOR, WDTNumber Of I /o32
Program Memory Size15KB (15K x 8)Program Memory TypeOTP
Eeprom Size256 x 8Ram Size352 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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Technical Data
M68HC05
Microcontrollers
MC68HC05B6/D
Rev. 4.1
08/2005
freescale.com

MC68HC705B16CFN Summary of contents

  • Page 1

    MC68HC05B4 MC68HC705B5 MC68HC05B5 MC68HC05B6 MC68HC05B8 MC68HC05B16 MC68HC705B16 MC68HC705B16N MC68HC05B32 MC68HC705B32 Technical Data M68HC05 Microcontrollers MC68HC05B6/D Rev. 4.1 08/2005 freescale.com ...

  • Page 2

    ...

  • Page 3

    MODES OF OPERATION AND PIN DESCRIPTIONS SERIAL COMMUNICATIONS INTERFACE PULSE LENGTH D/A CONVERTERS ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS INTRODUCTION MEMORY AND REGISTERS INPUT/OUTPUT PORTS PROGRAMMABLE TIMER RESETS AND INTERRUPTS MECHANICAL DATA ORDERING INFORMATION APPENDICES ...

  • Page 4

    INTRODUCTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS 3 MEMORY AND REGISTERS 4 INPUT/OUTPUT PORTS 5 PROGRAMMABLE TIMER 6 SERIAL COMMUNICATIONS INTERFACE 7 PULSE LENGTH D/A CONVERTERS 8 ANALOG TO DIGITAL CONVERTER 9 RESETS AND INTERRUPTS 10 CPU CORE ...

  • Page 5

    CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05B6/D rev. 4) Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication you have just received. Having used the document, please complete this card (or a photocopy ...

  • Page 6

    How could we improve this document? 9. How would you rate Motorola’s documentation? – In general – Against other semiconductor suppliers 10. Which semiconductor manufacturer provides the best technical documentation? 11. Which company (in any field) provides the best ...

  • Page 7

    High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit All Trade Marks recognized. This document contains information on new products. Specifications and information herein are subject to change without notice. All products are sold on Freescale’s Terms & Conditions of Supply. ...

  • Page 8

    Where abbreviations are used in the text, an explanation can be found in the glossary, at the back of this manual. Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low ...

  • Page 9

    TABLE OF CONTENTS Paragraph Number 1.1 Features.............................................................................................................1–2 1.2 Mask options for the MC68HC05B6 ..................................................................1–3 MODES OF OPERATION AND PIN DESCRIPTIONS 2.1 Modes of operation ............................................................................................2–1 2.1.1 Single chip mode .........................................................................................2–1 2.2 Serial RAM loader .............................................................................................2–2 2.3 ‘Jump to any address’........................................................................................2–4 ...

  • Page 10

    Paragraph Number 2.5.13 PLMB ......................................................................................................... 2–13 2.5.14 VPP1.......................................................................................................... 2–13 2.5.15 VRH ........................................................................................................... 2–13 2.5.16 VRL............................................................................................................ 2–13 2.5.17 PA0 – PA7/PB0 – PB7/PC0 – PC7 ............................................................ 2–13 2.5.18 PD0/AN0–PD7/AN7................................................................................... 2–13 3.1 Registers ........................................................................................................... 3–1 3.2 RAM .................................................................................................................. 3–1 3.3 ROM .................................................................................................................. ...

  • Page 11

    Paragraph Number 5.1 Counter ..............................................................................................................5–1 5.1.1 Counter register and alternate counter register ...........................................5–3 5.2 Timer control and status ....................................................................................5–4 5.2.1 Timer control register (TCR) ........................................................................5–4 5.2.2 Timer status register (TSR)..........................................................................5–6 5.3 Input capture......................................................................................................5–7 5.3.1 Input capture register 1 (ICR1) ....................................................................5–7 ...

  • Page 12

    Paragraph Number PULSE LENGTH D/A CONVERTERS 7.1 Miscellaneous register....................................................................................... 7–3 7.2 PLM clock selection........................................................................................... 7–4 7.3 PLM during STOP mode ................................................................................... 7–4 7.4 PLM during WAIT mode .................................................................................... 7–4 ANALOG TO DIGITAL CONVERTER 8.1 A/D converter operation..................................................................................... 8–1 8.2 A/D ...

  • Page 13

    Paragraph Number CPU CORE AND INSTRUCTION SET 10.1 Registers .........................................................................................................10–1 10.1.1 Accumulator (A) .........................................................................................10–2 10.1.2 Index register (X)........................................................................................10–2 10.1.3 Program counter (PC) ................................................................................10–2 10.1.4 Stack pointer (SP) ......................................................................................10–2 10.1.5 Condition code register (CCR)...................................................................10–2 10.2 Instruction set ..................................................................................................10–3 10.2.1 Register/memory Instructions ...

  • Page 14

    Paragraph Number 12.1.3 56-pin shrink dual in line package (SDIP).................................................. 12–3 12.2 MC68HC05B6 mechanical dimensions ........................................................... 12–4 12.2.1 52-pin plastic leaded chip carrier (PLCC) .................................................. 12–4 12.2.2 64-pin quad flat pack (QFP)....................................................................... 12–5 12.2.3 56-pin shrink dual in line package ...

  • Page 15

    Paragraph Number D.1 Features............................................................................................................ D–1 D.2 Self-check routines ........................................................................................... D–2 D.3 External clock ................................................................................................... D–4 E.1 Features............................................................................................................ E–2 E.2 External clock ................................................................................................... E–5 E.3 EPROM............................................................................................................. E–5 E.3.1 EPROM read operation............................................................................... E–5 E.3.2 EPROM program operation......................................................................... E–5 E.3.3 EPROM/EEPROM/ECLK control register ...

  • Page 16

    Paragraph Number F.5.2 EPROM/EEPROM parallel bootstrap.........................................................F–13 F.5.3 Serial RAM loader......................................................................................F–16 F.5.3.1 Jump to start of RAM ($0051) ..............................................................F–16 F.6 Absolute maximum ratings ..............................................................................F–19 F.7 DC electrical characteristics ............................................................................F–20 F.8 A/D converter characteristics ..........................................................................F–22 F.9 Control timing ..................................................................................................F–24 F.10 EPROM electrical ...

  • Page 17

    LIST OF FIGURES Figure Number 1-1 MC68HC05B6 block diagram ............................................................................. 1–3 2-1 MC68HC05B6 ‘load program in RAM and execute’ schematic diagram ............ 2–3 2-2 MC68HC05B6 ‘jump to any address’ schematic diagram .................................. 2–5 2-3 STOP and WAIT flowcharts................................................................................ 2–7 2-4 ...

  • Page 18

    Figure Number 10-1 Programming model ......................................................................................... 10–1 10-2 Stacking order .................................................................................................. 10–1 11-1 Run I vs internal operating frequency (4.5V, 5.5V) ...................................... 11–3 DD 11-2 Run I ( internal operating frequency (4.5V, 5.5V) ....................... 11–3 DD 11-3 ...

  • Page 19

    Figure Number E-4 Modes of operation flow chart ( ..............................................................E–12 E-5 Timing diagram with handshake .......................................................................E–14 E-6 Parallel EPROM loader timing diagram ............................................................E–14 E-7 EPROM Parallel bootstrap schematic diagram.................................................E–15 E-8 RAM/EPROM/EEPROM serial bootstrap schematic diagram ..........................E–17 E-9 Parallel ...

  • Page 20

    THIS PAGE LEFT BLANK INTENTIONALLY Freescale xii LIST OF FIGURES MC68HC05B6 Rev. 4.1 ...

  • Page 21

    LIST OF TABLES Table Number 1-1 Data sheet appendices....................................................................................... 1–1 2-1 Mode of operation selection ............................................................................... 2–1 3-1 EEPROM control bits description ....................................................................... 3–4 3-2 Register outline................................................................................................... 3–8 3-3 IRQ sensitivity..................................................................................................... 3–9 4-1 I/O pin states ...................................................................................................... 4–2 6-1 Method ...

  • Page 22

    Table Number 13-1 MC order numbers ........................................................................................... 13–1 13-2 EPROMs for pattern generation ....................................................................... 13–2 A-1 Mode of operation selection ...............................................................................A–1 A-2 Register outline ..................................................................................................A–4 A-3 MC68HC05B4 self-check results .......................................................................A–6 B-1 Register outline ..................................................................................................B–4 C-1 Register outline ..................................................................................................C–4 C-2 Mode ...

  • Page 23

    Table Number F-15 Control timing for 3.3V operation ......................................................................F–26 G-1 Register outline.................................................................................................. G–4 H-1 Register outline.................................................................................................. H–6 H-2 EPROM control bits description......................................................................... H–9 H-3 EEPROM control bits description .................................................................... H–10 H-4 Mode of operation selection ............................................................................ H–13 H-5 Bootstrap vector ...

  • Page 24

    THIS PAGE LEFT BLANK INTENTIONALLY Freescale xvi LIST OF TABLES MC68HC05B6 Rev. 4.1 ...

  • Page 25

    INTRODUCTION The MC68HC05B6 microcomputer (MCU member of Freescale’s MC68HC05 family of low-cost single chip microcomputers. This 8-bit MCU contains an on-chip oscillator, CPU, RAM, ROM, EEPROM, A/D converter, pulse length modulated outputs, I/O, serial communications interface, programmable timer ...

  • Page 26

    Features Hardware features • Fully static design featuring the industry standard M68HC05 family CPU core • On chip crystal oscillator with divide software selectable divide by 32 option (SLOW mode) • 2.1 MHz internal ...

  • Page 27

    Mask options for the MC68HC05B6 The MC68HC05B6 has three mask options that are programmed during manufacture and must be specified on the order form. • Power-on-reset delay ( 4064 cycles PORL • Automatic watchdog enable/disable ...

  • Page 28

    THIS PAGE LEFT BLANK INTENTIONALLY Freescale 1-4 INTRODUCTION MC68HC05B6 Rev. 4.1 ...

  • Page 29

    MODES OF OPERATION AND PIN DESCRIPTIONS 2.1 Modes of operation The MC68HC05B6 MCU has two modes of operation, namely single chip and self check modes. Table 2-1 shows the conditions required to enter each mode on the rising edge of ...

  • Page 30

    Serial RAM loader 2 The ‘load program in RAM and execute’ mode is entered if the following conditions are satisfied when the reset pin is released to V MC68HC805C4. The SEC bit in the options register must be inactive, ...

  • Page 31

    RESET 18 RESET 0.01 µ 9600 Bd 50 RS232 level translator RDI suggested: 52 TDO RS232 MC145406 or MAX232 24 PA7 25 PA6 26 PA5 27 PA4 28 PA3 29 PA2 30 PA1 31 ...

  • Page 32

    The ‘jump to any address’ mode is entered when the reset pin is released to V conditions are satisfied: – IRQ at 2xV DD – TCAP1 – PD3 at V for ...

  • Page 33

    RESET 18 RESET 0.01 µ kΩ optional (see note) 24 PA7 25 PA6 26 PA5 27 PA4 28 PA3 29 PA2 30 PA1 31 PA0 kΩ 32 PB7 ...

  • Page 34

    Low power modes 2 The STOP and WAIT instructions have different effects on the programmable timer, the serial communications interface, the watchdog system, the EEPROM and the A/D converter. These different effects are described in the following sections. 2.4.1 ...

  • Page 35

    STOP YES Watchdog active? Stop oscillator and all clocks. Clear I bit. NO Reset? IRQ NO external interrupt? YES Turn on oscillator. Wait for time delay to stabilise Generate watchdog reset (1) Fetch reset vector or (2) Service interrupt: a. ...

  • Page 36

    WAIT 2 The WAIT instruction places the MCU in a low power consumption mode, but WAIT mode consumes more power than STOP mode. All CPU action is suspended and the watchdog is disabled, but the timer, A/D and SCI ...

  • Page 37

    SLOW mode The SLOW mode function is controlled by the SM bit in the miscellaneous register at location $000C. It allows the user to insert, under software control, an extra divide-by-16 between the oscillator and the internal clock driver ...

  • Page 38

    Pin descriptions 2 2.5.1 VDD and VSS Power is supplied to the microcontroller using these two pins. VDD is the positive supply and VSS is ground the nature of CMOS designs that very fast signal transitions ...

  • Page 39

    TCAP2 The TCAP2 input controls the input capture 2 function of the on-chip programmable timer system. 2.5.6 TCMP1 The TCMP1 pin is the output of the output compare 1 function of the timer system. 2.5.7 TCMP2 The TCMP2 pin ...

  • Page 40

    External clock 2 An external clock should be applied to the OSC1 input, with the OSC2 pin left unconnected, as shown in Figure 2-5(c). The t using an external clock input. The equivalent specification of the external clock source ...

  • Page 41

    RDI (Receive data in) The RDI pin is the input pin of the SCI receiver. 2.5.10 TDO (Transmit data out) The TDO pin is the output pin of the SCI transmitter. 2.5.11 SCLK The SCLK pin is the clock ...

  • Page 42

    THIS PAGE LEFT BLANK INTENTIONALLY Freescale MODES OF OPERATION AND PIN DESCRIPTIONS 2-14 MC68HC05B6 Rev. 4.1 ...

  • Page 43

    MEMORY AND REGISTERS The MC68HC05B6 MCU is capable of addressing 8192 bytes of memory and registers with its program counter. The memory map includes 5950 bytes of User ROM (including User vectors), 432 bytes of self check ROM, 176 bytes ...

  • Page 44

    Self-check ROM There are two areas of self-check ROM (ROMI and ROMII) located from $0200 to $02BF (192 bytes) and $1F00 to $1FEF (240 bytes) respectively. 3 MC68HC05B6 $0000 I/O (32 bytes) $0020 Page 0 User ROM (48 bytes) ...

  • Page 45

    EEPROM The user EEPROM consists of 256 bytes of memory located from address $0100 to $01FF. 255 bytes are general purpose and 1 byte is used by the option register. The non-volatile EEPROM is byte erasable. An internal charge ...

  • Page 46

    E1LAT — EEPROM programming latch enable bit 1 (set) – Address and data can be latched into the EEPROM for further program or erase operations, providing the E1PGM bit is cleared. 0 (clear) – Data can be read from the ...

  • Page 47

    EEPROM read operation To be able to read from EEPROM, the E1LAT bit has logic zero, as shown in While this bit is at logic zero, the E1PGM bit and the E1ERA bit are permanently reset ...

  • Page 48

    EEPROM programming operation To program a byte of EEPROM, the following steps should be taken: 1 Set the E1LAT bit Write address/data to the EEPROM address to be programmed. 3 Set the E1PGM bit. 4 Wait for ...

  • Page 49

    EE1P – EEPROM protect bit In order to achieve a higher degree of protection, the EEPROM is effectively split into two parts, both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to ...

  • Page 50

    Register name Port A data (PORTA) 3 Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC) EEPROM/ECLK control A/D data (ADDATA) A/D ...

  • Page 51

    Miscellaneous register Address Miscellaneous $000C POR (1) The POR bit is set each time there is a power-on reset. (2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled. ...

  • Page 52

    SFA — Slow or fast mode selection for PLMA (see This bit allows the user to select the slow or fast mode of the PLMA pulse length modulation output. 1 (set) – Slow mode PLMA (4096 x timer clock period). ...

  • Page 53

    INPUT/OUTPUT PORTS In single-chip mode, the MC68HC05B6 has a total of 24 I/O lines, arranged as three 8-bit ports (A, B and C), and eight input-only lines, arranged as one 8-bit port (D). Each I/O line is individually programmable as ...

  • Page 54

    Data direction register bit Latched data register bit 4 Table 4-1 shows the effect of reading from or writing to an I/O pin in various circumstances. Note that the read/write signal shown is internal and not available to the user. ...

  • Page 55

    Port C In addition to the standard port functions described for port A and B, port C pin 2 can be configured, using the ECLK bit of the EEPROM/ECLK control register, to output the CPU clock. If this is ...

  • Page 56

    D with levels other than V power dissipation during the read cycle. As port input-only port there is no DDR associated with it. Also, at power up or external reset, the A/D ...

  • Page 57

    Port data register D (PORTD) Address Port D data (PORTD) $0003 All the port D bits are input-only and are shared with the A/D converter. The function of each bit is determined by the ADON bit in the A/D ...

  • Page 58

    Other port considerations All output ports can emulate ‘open-drain’ outputs. This is achieved by writing a zero to the relevant output port latch. By toggling the corresponding data direction bit, the port pin will either be an output zero ...

  • Page 59

    PROGRAMMABLE TIMER The programmable timer on the MC68HC05B6 consists of a 16-bit read-only free-running counter, with a fixed divide-by-four prescaler, plus the input capture/output compare circuitry. The timer can be used for many purposes including measuring pulse length of two ...

  • Page 60

    High Low High byte byte Output $0016 compare compare $0017 register 1 register PLM Output compare compare circuit 1 circuit ICF1 OCF1 TOF ICF2 Interrupt circuit Input capture interrupt $1FF8,9 Figure 5-1 ...

  • Page 61

    Counter register and alternate counter register Address Timer counter high $0018 Timer counter low $0019 Address Alternate counter high $001A Alternate counter low $001B The double-byte, free-running counter can be read from either of two locations, $18-$19 (counter register) ...

  • Page 62

    Timer control and status The various functions of the timer are monitored and controlled using the timer control and status registers described below. 5.2.1 Timer control register (TCR) The timer control register ($0012) is used to enable the input ...

  • Page 63

    FOLV2 — Force output compare 2 This bit always reads as zero, hence writing a zero to this bit has no effect. Writing a one at this position will force the OLV2 bit to the corresponding output level latch, thus ...

  • Page 64

    Timer status register (TSR) The timer status register ($13 read only register and contains the status bits corresponding to the four timer interrupt conditions – ICF1,OCF1, TOF, ICF2 and OCF2. Accessing the timer status register satisfies the ...

  • Page 65

    ICF2 — Input capture flag 2 This bit is set when a negative edge is detected by the input capture edge detector 2 at TCAP2; an input capture interrupt will be generated if ICIE is set. ICF2 is cleared by ...

  • Page 66

    The result obtained from an input capture will be one greater than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. This delay is required for internal synchronization. Resolution is ...

  • Page 67

    Output compare ‘Output compare’ technique which may be used, for example, to generate an output waveform signal when a specific time period has elapsed, by presetting the output compare register to the appropriate value. There ...

  • Page 68

    The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read and the write to the corresponding output compare register. All bits of the output compare register are readable and writable ...

  • Page 69

    The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read and the write to the corresponding output compare register. All bits of the output compare register are readable and writable ...

  • Page 70

    Timer during STOP mode When the MCU enters STOP mode, the timer counter stops counting and remains at that particular count value until STOP mode is exited by an interrupt. If STOP mode is exited by power-on or external ...

  • Page 71

    Internal processor clock Internal reset  T00  T01  Internal timer clocks T10   T11 16-bit counter External reset or end of POR Note: The counter and timer control registers are the only ones affected by power-on or ...

  • Page 72

    Internal processor clock    Internal timer clocks   16-bit counter Output compare register 5 Compare register latch Output compare flag and TCMP1,2 Note: 1 The CPU write to the compare registers may take place at any time, ...

  • Page 73

    SERIAL COMMUNICATIONS INTERFACE A full-duplex asynchronous serial communications interface (SCI) is provided with a standard non-return-to-zero (NRZ) format and a variety of baud rates. The SCI transmitter and receiver are functionally independent and have their own baud rate generator; however ...

  • Page 74

    Transmit $0011 data register (See note) Transmit TDO data shift pin register 6 Transmitter clock Clock extraction SCLK phase and pin polarity control Note: The serial communications data register (SCI SCDR) is controlled by the internal R/W signal ...

  • Page 75

    SCI receiver features • Receiver wake-up function (idle line or address bit) • Idle line detection • Framing error detection • Noise detection • Overrun detection • Receiver data register full flag 6.3 SCI transmitter features • Transmit data ...

  • Page 76

    When SCDR is read, it contains the last data byte received, provided that the receiver is enabled. The receive data register full flag bit (RDRF) in the SCSR is set to indicate that a data byte has been transferred from ...

  • Page 77

    Data format Receive data or transmit data is the serial data that is transferred to the internal data bus from the receive data input pin (RDI) or from the internal bus to the transmit data output pin (TDO). The ...

  • Page 78

    Idle line wake-up In idle line wake-up mode, a dormant receiver wakes up as soon as the RDI line becomes idle. Idle is defined as a continuous logic high level on the RDI line for ten (or eleven) full ...

  • Page 79

    RT clock edges for all three examples Idle RDI RDI Noise RDI Figure 6-4 SCI examples of start ...

  • Page 80

    If the receiver detects that a break (RDRF = receiver data register = $0000) produced the framing error, the start bit will not be artificially induced and the receiver must actually detect a logic one before ...

  • Page 81

    SCI synchronous transmission The SCI transmitter allows the user to control a one way synchronous serial transmission. The SCLK pin is the clock output of the SCI transmitter. No clocks are sent to that pin during start bit and ...

  • Page 82

    SCI registers The SCI system is configured and controlled by five registers: SCDR, SCCR1, SCCR2, SCSR, and BAUD. 6.11.1 Serial communications data register (SCDR) SCI data (SCDR) The SCDR is controlled by the internal R/W signal and performs two ...

  • Page 83

    R8 — Receive data bit 8 This read-only bit is the ninth serial data bit received when the SCI system is configured for nine data bit operation (M = 1). The most significant bit (bit 8) of the received character ...

  • Page 84

    CPOL – Clock polarity This bit allows the user to select the polarity of the clocks to be sent to the SCLK pin. It works in conjunction with the CPHA bit to produce the desired clock-data relation (see Figure 6-10). ...

  • Page 85

    Idle or preceding transmission Start clock (CPOL = 0, CPHA = 0) clock (CPOL = 0, CPHA = 1) clock (CPOL = 1, CPHA = 0) clock (CPOL = 1, CPHA = 1) data 0 Start LSB Figure 6-10 SCI ...

  • Page 86

    Serial communications control register 2 (SCCR2) The SCI control register 2 (SCCR2) provides the control bits that enable/disable individual SCI functions. SCI control (SCCR2) TIE — Transmit interrupt enable 1 (set) – TDRE interrupts enabled. 0 (clear) – TDRE ...

  • Page 87

    After loading the last byte in the serial communications data register and receiving the TDRE flag, the user should clear TE. Transmission of the last byte will then be completed and the line will go idle. 1 (set) – Transmitter ...

  • Page 88

    Serial communications status register (SCSR) SCI status (SCSR) The serial communications status register (SCSR) provides inputs to the interrupt logic circuits for generation of the SCI system interrupt. In addition, a noise flag bit and a framing error bit ...

  • Page 89

    OR — Overrun error flag This bit is set when a new byte is ready to be transferred from the receiver shift register to the receiver data register and the receive data register is already full (RDRF bit is set). ...

  • Page 90

    Baud rate register (BAUD) The baud rate register provides the means to select two different or equivalent baud rates for the transmitter and receiver. SCI baud rate (BAUD) SCP1, SCP0 — Serial prescaler select bits These read/write bits determine ...

  • Page 91

    SCR2, SCR1, SCR0 — SCI rate select bits (receiver) These three read/write bits select the baud rates for the receiver. The prescaler output described above is divided by the factors shown in Table 6-5 Second prescaler stage (receiver) SCR2 0 ...

  • Page 92

    SCP1 SCP0 SCT/R2 SCT/R1 SCT/ ...

  • Page 93

    SCI during STOP mode When the MCU enters STOP mode, the baud rate generator driving the receiver and transmitter is shut down. This stops all SCI activity. Both the receiver and the transmitter are unable to operate. If the ...

  • Page 94

    THIS PAGE LEFT BLANK INTENTIONALLY Freescale 6-22 SERIAL COMMUNICATIONS INTERFACE MC68HC05B6 Rev. 4.1 ...

  • Page 95

    PULSE LENGTH D/A CONVERTERS The pulse length D/A converter (PLM) system works in conjunction with the timer to execute two 8-bit D/A conversions, with a choice of two repetition rates. (See PLMA R D/A Latch pin S Zero detector SFA ...

  • Page 96

    The D/A converter has two data registers associated with it, PLMA and PLMB. Pulse length modulation A (PLMA) Pulse length modulation B (PLMB) This is a dual 8-bit resolution D/A converter associated with two output pins (PLMA and PLMB). The ...

  • Page 97

    Note: Since the PLM system uses the timer counter, PLM results will be affected while resetting the timer counter. Both D/A registers are reset to $00 during power-on or external reset. WAIT mode does not affect the output waveform of ...

  • Page 98

    The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when entering STOP mode. Note: The bits that are shown shaded in the above representation are explained individually in the relevant sections of this ...

  • Page 99

    ANALOG TO DIGITAL CONVERTER The analog to digital converter system consists of a single 8-bit successive approximation converter and a sixteen channel multiplexer. Eight of the channels are connected to the PD0/AN0 – PD7/AN7 pins of the MC68HC05B6 and the ...

  • Page 100

    The A/D reference input (AN0–AN7) is applied to a precision internal D/A converter. Control logic drives this D/A converter and the analog output is successively compared with the analog input sampled at the beginning of the conversion. The conversion is ...

  • Page 101

    A/D registers 8.2.1 Port D data register (PORTD) Address Port D data (PORTD) $0003 Port input-only port which routes the eight analog inputs to the A/D converter. When the A/D converter is disabled, the pins are ...

  • Page 102

    A/D status/control register (ADSTAT) A/D status/control (ADSTAT) COCO — Conversion complete flag 1 (set) – COCO is set each time a conversion is complete, allowing the new result to be read from the A/D result data register ($08). The ...

  • Page 103

    ADON — A/D converter on The ADON bit allows the user to enable/disable the A/D converter. 1 (set) – A/D converter is switched on. 0 (clear) – A/D converter is switched off. When the A/D converter is switched on, it ...

  • Page 104

    A/D converter during STOP mode When the MCU enters STOP mode with the A/D converter turned on, the A/D clocks are stopped and the A/D converter is disabled for the duration of STOP mode, including the 4064 cycles start-up ...

  • Page 105

    RESETS AND INTERRUPTS 9.1 Resets The MC68HC05B6 can be reset in three ways: by the initial power-on reset function active low input to the RESET pin computer operating properly (COP) watchdog reset. Any of these ...

  • Page 106

    Power-on reset A power-on reset occurs when a positive transition is detected on VDD. The power-on reset function is strictly for power turn-on conditions and should not be used to detect drops in the power supply voltage. The power-on ...

  • Page 107

    RESET pin When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied to the RESET input for a minimum period of 1.5 machine cycles (t is used to improve noise ...

  • Page 108

    WDOG bit has no effect at any time). In addition, the WDOG bit acts as a reset mechanism for the watchdog counter. Writing a ‘1’ to this bit clears the ...

  • Page 109

    Functions affected by reset When processing stops within the MCU for any reason, i.e. power-on reset, external reset or the execution of a STOP or WAIT instruction, various internal functions of the MCU are affected. Table 9-1 shows the ...

  • Page 110

    Interrupts The MCU can be interrupted by four different sources: three maskable hardware interrupts and one non maskable software interrupt: • External signal on the IRQ pin • Serial communications interface (SCI) • Programmable timer • Software interrupt instruction ...

  • Page 111

    Source Reset Software interrupt (SWI) External interrupt (IRQ) Timer input captures Timer output compares Timer overflow Serial communications interface (SCI) generated after the SWI was fetched. The SWI interrupt service routine address is specified by the contents of memory locations ...

  • Page 112

    Reset Is I-bit set? external interrupt? Timer internal interrupt? 9 internal interrupt? Fetch next instruction Execute instruction Freescale 9-8 IRQ Clear IRQ request latch SCI Figure 9-3 Interrupt flow chart RESETS AND INTERRUPTS Stack PC Set I-bit ...

  • Page 113

    Miscellaneous register Address Miscellaneous $000C Note: The bits shown shaded in the above representation are explained individually in the relevant sections of this manual. The complete register plus an explanation of each bit can be found in Section INTP, ...

  • Page 114

    Timer interrupts There are five different timer interrupt flags (ICF1, ICF2, OCF1, OCF2 and TOF) that will cause a timer interrupt whenever they ...

  • Page 115

    Hardware controlled interrupt sequence The following three functions: reset, STOP and WAIT, are not in the strictest sense interrupts. However, they are acted upon in a similar manner. Flowcharts for STOP and WAIT are shown in RESET: A reset ...

  • Page 116

    THIS PAGE LEFT BLANK INTENTIONALLY 9 Freescale 9-12 RESETS AND INTERRUPTS MC68HC05B6 Rev. 4.1 ...

  • Page 117

    CPU CORE AND INSTRUCTION SET This section provides a description of the CPU core registers, the instruction set and the addressing modes of the MC68HC05B6. 10.1 Registers The MCU contains five registers, as shown in the programming model of stacking ...

  • Page 118

    Accumulator (A) The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 10.1.2 Index register (X) The index register is an 8-bit register, which can contain the indexed addressing ...

  • Page 119

    Half carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Interrupt (I) When this bit is set all maskable interrupts are masked interrupt occurs while ...

  • Page 120

    Register/memory Instructions Most of these instructions use two operands. The first operand is either the accumulator or the index register. The second operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump ...

  • Page 121

    Operation Description Condition codes Source Form Table 10-2 Register/memory instructions Function Load A from memory LDA A6 Load X from memory LDX AE Store A in memory STA Store X in memory STX Add memory to A ADD AB Add ...

  • Page 122

    Branch always Branch never Branch if higher Branch if lower or same Branch if carry clear (Branch if higher or same) Branch if carry set (Branch if lower) Branch if not equal Branch if equal Branch if half carry clear ...

  • Page 123

    Table 10-5 Read/modify/write instructions Function Increment INC Decrement DEC Clear CLR Complement COM Negate (two’s complement) NEG Rotate left through carry ROL Rotate right through carry ROR Logical shift left LSL Logical shift right LSR Arithmetic shift right ASR Test ...

  • Page 124

    Mnemonic INH ADC ADD AND ASL ASR BCC BCLR BCS BEQ BHCC BHCS BHI BHS BIH BIL BIT BLO BLS BMC BMI BMS BNE BPL BRA BRN 10 BRCLR BRSET BSET BSR CLC CLI CLR CMP Address mode abbreviations BSC ...

  • Page 125

    Table 10-8 Instruction set ( Mnemonic INH IMM DIR COM CPX DEC EOR INC JMP JSR LDA LDX LSL LSR MUL NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STOP STX SUB SWI TAX ...

  • Page 126

    Freescale 10-10 Table 10-9 M68HC05 opcode map CPU CORE AND INSTRUCTION SET MC68HC05B6 Rev. 4.1 ...

  • Page 127

    Addressing modes Ten different addressing modes provide programmers with the flexibility to optimize their code for all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the ...

  • Page 128

    Extended In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. Instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte ...

  • Page 129

    Relative The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only if, the branch conditions are ...

  • Page 130

    THIS PAGE LEFT BLANK INTENTIONALLY 10 Freescale 10-14 CPU CORE AND INSTRUCTION SET MC68HC05B6 Rev. 4.1 ...

  • Page 131

    ELECTRICAL SPECIFICATIONS This section contains the electrical specifications and associated timing information for the MC68HC05B6. 11.1 Absolute maximum ratings Table 11-1 Absolute maximum ratings Rating (1) Supply voltage Input voltage (Except V ) PP1 Input voltage – Self-check mode (IRQ ...

  • Page 132

    DC electrical characteristics Table 11-2 DC electrical characteristics for 5V operation = 5 Vdc ± 10 Characteristic Output voltage = – 10 µA I LOAD = +10 µA I LOAD Output high voltage (I LOAD PA0–7, ...

  • Page 133

    I trends for 5V operation DD For the examples below, typical values are at the mid-point of the voltage range and at a temperature of 25°C only (mA ...

  • Page 134

    I (mA) 0.4 DD 0.3 0.2 0 Figure 11-4 Wait I 1.6 1.4 1.2 1 0.8 I (mA) 0.6 DD 0.4 0 Figure 11-5 Increase ...

  • Page 135

    Table 11-3 DC electrical characteristics for 3.3V operation = 3.3Vdc ± 10 0Vdc (1) Characteristic Output voltage = – 10 µA I LOAD = +10 µA I LOAD Output high voltage (I = 0.2mA) ...

  • Page 136

    I trends for 3.3V operation DD For the examples below, typical values are at the mid-point of the voltage range and at a temperature of 25°C only. 2.5 2 1.5 I (mA 0 Figure 11-7 ...

  • Page 137

    I (mA) DD 0.2 0 0.5 Figure 11-10 Wait I DD 0.7 0.6 0.5 I (mA) 0.4 DD 0.3 0.2 0 0.5 Figure 11-11 Increase in I 2.5 2 1.5 I (mA) DD ...

  • Page 138

    A/D converter characteristics = 5.0 Vdc ± 10 Characteristic Resolution Non-linearity Quantization error Absolute accuracy Conversion range (1) ∆V R Conversion time Monotonicity Zero input reading Full scale reading Sample acquisition ...

  • Page 139

    Table 11-5 A/D characteristics for 3.3V operation = 3.3 Vdc ± 10 Vdc Characteristic Resolution Number of bits resolved by the A/D Non-linearity Max deviation from the best straight line through the ...

  • Page 140

    Control timing = 5.0 Vdc ± 10 Frequency of operation Crystal option External clock option Internal operating frequency (f Using crystal Using external clock Cycle time (see Crystal oscillator start-up time (see Stop recovery start-up time ...

  • Page 141

    Table 11-7 Control timing for 3.3V operation = 3.3Vdc ± 10 Characteristic Frequency of operation Crystal option External clock option Internal operating frequency (f Using crystal Using external clock Cycle time (see Figure 9-1) Crystal oscillator ...

  • Page 142

    External signal (TCAP1, TCAP2) 11 Freescale 11- TLTL TH Figure 11-13 Timer relationship ELECTRICAL SPECIFICATIONS t TL MC68HC05B6 Rev. 4.1 ...

  • Page 143

    MECHANICAL DATA 12.1 MC68HC05B family pin configurations 12.1.1 52-pin plastic leaded chip carrier (PLCC) VRH 8 PD4/AN4 9 VDD 10 PD3/AN3 11 PD2/AN2 12 PD1/AN1 13 PD0/AN0 14 NC/VPP6 15 OSC1 16 OSC2 17 RESET 18 IRQ 19 PLMA 20 ...

  • Page 144

    SCLK TCMP2 TCMP1 PD7/AN7 PD6/AN6 PD5/AN5 12 Figure 12-2 64-pin QFP pinout for the MC68HC05B6 Freescale 12-2 PC1 1 PC0 RDI 8 9 ...

  • Page 145

    TCMP1 NC/NU NC/VPP6 OSC1 OSC2 RESET PLMA PLMB TCAP1 TCAP2 Device MC68HC05B4 MC68HC05B6 MC68HC05B8 MC68HC05B16 MC68HC05B32 MC68HC705B5 MC68HC705B16 MC68HC705B16N MC68HC705B32 NC = Not connected NU = Non-user pin (Should be tied to ...

  • Page 146

    MC68HC05B6 mechanical dimensions 12.2.1 52-pin plastic leaded chip carrier (PLCC) –L– pin 52 C 0.25 S Dim. Min. Max. A 19.94 20.19 B 19.94 20.19 C 4.20 4. 2.29 2.79 F 0.33 0.48 G 1.27 BSC H ...

  • Page 147

    Case No. 840C L 64 lead QFP Detail “A” 0. – 0.05 A – B ...

  • Page 148

    T - Seating Plane D 0.25 Dim. Min. Max. A 51.69 52.45 B 13.72 14.22 C 3.94 5.08 D 0.36 0.56 E 0.89 BSC F 0.81 1.17 G 1.778 ...

  • Page 149

    ORDERING INFORMATION This section describes the information needed to order the MC68HC05B6 and other family members. To initiate a ROM pattern for the MCU necessary to contact your local field service office, local sales person or Freescale representative. ...

  • Page 150

    EPROMS For the MC68HC05B6 kbyte EPROM programmed with the customer’s software (positive logic for address and data) should be submitted for pattern generation. All unused bytes should be programmed to $00. The size of EPROM which should ...

  • Page 151

    The MC68HC05B4 is a device similar to the MC68HC05B6, but without EEPROM and having a reduced ROM size of 4 kbytes. The entire MC68HC05B6 data sheet applies to the MC68HC05B4, with the exceptions outlined in this appendix. A.1 Features • ...

  • Page 152

    RESET IRQ OSC2 OSC1 VDD VSS PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL PLMA D/A PLMB D/A 14 Freescale A-2 COP watchdog 4158 bytes Oscillator User ROM (including 14 bytes ÷ ÷ User vectors) ...

  • Page 153

    MC68HC05B4 $0000 I/O (32 bytes) $0020 Page 0 User ROM (48 bytes) $0050 RAM (176 bytes) $00C0 Stack $0100 $0200 Self-check ROM I (192 bytes) $02C0 $0F00 User ROM (4096 bytes) $1F00 Self-check ROM II (240 bytes) $1FF0 $1FF2–3 SCI ...

  • Page 154

    Register name Port A data (PORTA) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC) ECLK control A/D data (ADDATA) A/D status/control ...

  • Page 155

    A.2 Self-check mode The self-check function available on the MC68HC05B4 provides an internal capability to determine if the device is functional. Self-check is performed using the circuit shown in Port C pins PC0–PC3 are monitored for the self-check results (light ...

  • Page 156

    Freescale A-6 Table A-3 MC68HC05B4 self-check results PC3 PC2 PC1 PC0 Bad port Bad port Bad RAM Bad ROM ...

  • Page 157

    RESET NC 18 RESET 0.01 µ VPP1 50 RDI 52 TDO 20 PLMA 21 PLMB 2 TCMP1 51 SCLK 3 PD7 4 PD6 5 PD5 9 PD4 11 PD3 12 PD2 13 PD1 14 PD0 24 ...

  • Page 158

    THIS PAGE LEFT BLANK INTENTIONALLY 14 Freescale A-8 MC68HC05B4 MC68HC05B6 Rev. 4.1 ...

  • Page 159

    The MC68HC05B8 is a device similar to the MC68HC05B6, but with an increased ROM size of 7.25 kbytes. The entire MC68HC05B6 data sheet applies to the MC68HC05B8, with the exceptions outlined in this appendix. B.1 Features • 7230 bytes User ...

  • Page 160

    VPP1 RESET IRQ OSC2 OSC1 VDD VSS PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL 14 Freescale B-2 256 bytes EEPROM 7230 bytes User ROM Charge pump (including 14 bytes User vectors) COP watchdog Oscillator ÷ ÷ 2 ...

  • Page 161

    MC68HC05B8 $0000 I/O (32 bytes) $0020 Page 0 User ROM (48 bytes) $0050 RAM (176 bytes) $00C0 Stack $0100 OPTR (1 byte) $0101 Non protected (31 bytes) $0120 EEPROM (256 bytes) Protected (224 bytes) $0200 Self-check ROM I (192 bytes) ...

  • Page 162

    Register name Port A data (PORTA) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC) EEPROM/ECLK control A/D data (ADDATA) A/D status/control ...

  • Page 163

    MC68HC705B5 The MC68HC705B5 is a device similar to the MC68HC05B6, but with the 6 kbytes ROM and 256 bytes EEPROM replaced by a single EPROM array. In addition, the self-check routines available on the MC68HC05B6 are replaced by bootstrap firmware. ...

  • Page 164

    VPP6 RESET IRQ OSC2 OSC1 VDD VSS PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 PD4/AN4 PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL 14 Freescale C-2 256 bytes EPROM1 6206 bytes 496 bytes EPROM bootstrap ROM (including 14 bytes User vectors) COP watchdog Oscillator ÷ ÷ ...

  • Page 165

    MC68HC705B5 $0000 I/O (32 bytes) $0020 Page 0 User EPROM (48 bytes) $0050 RAM (176 bytes) $00C0 Stack $0100 User EPROM1 (256 bytes) $0200 Bootstrap ROMI (256 bytes) $0300 $0800 User EPROM (5888 bytes) $1EFE Options register $1F00 Bootstrap ROMII ...

  • Page 166

    Register name Port A data (PORTA) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC) EPROM/ECLK control A/D data (ADDATA) A/D status/control ...

  • Page 167

    C.2 EPROM The MC68HC705B5 has a total of 6206 bytes of EPROM, 256 bytes being reserved for the EPROM1 array (see Figure C-2). The EPP bit (EPROM protect) is not operative on the EPROM1 array, making it possible to program ...

  • Page 168

    C.3 EPROM registers C.3.1 EPROM control register EPROM/ECLK control (1) This bit is a copy of the EPP bit in the options register at $1EFE and therefore its state on reset will be the same as that for the EPP ...

  • Page 169

    C.4 Options register (OPTR) Address (1) Options (OPTR) $1EFE (1) This register is implemented in EPROM, therefore reset has no effect on the state of the individual bits. Note: This register can only be written to while the device is ...

  • Page 170

    The watchdog will be active during WAIT mode. 0 (clear) – The watchdog system will be disabled during WAIT mode. PBPD – Port B pull-down resistors 1 (set) – Pull-down resistors are connected to all 8 pins ...

  • Page 171

    The bootstrap program first copies part of itself into RAM, as the program cannot be executed in ROM during verification/programming of the EPROM. It then sets the TCMP1 output to a logic high level. Reset IRQ at 9V? Y TCAP1 ...

  • Page 172

    Bootstrap RAM PD4 set? Y Load next RAM byte N RAM full? Y Execute RAM program at $0050 14 Freescale C- Transmit last four programmed locations Receive address Receive four data Y Green LED on Execute RAM Program ...

  • Page 173

    C.5.1 Erased EPROM verification The flowchart in Figure C-3 and Figure C-4 to check if the EPROM is erased (all $00s non $00 byte is detected, the red LED stays on and the routine will stay in a ...

  • Page 174

    VPP 27C64 A10 23 A11 2 A12 GND 14 Note: This circuit is recommended for programming only at 25°C and not for use in the end application temperatures ...

  • Page 175

    C.5.3 EPROM (RAM) serial bootstrap load and execute The serial routine communicates through the SCI with an external host, typically a PC, by means of an RS232 link at 9600 baud, 8-bit, no parity and full duplex. Data format is ...

  • Page 176

    A 10-byte stack is also reserved at the top of the RAM allowing, for example, one interrupt and two sub-routine levels. Program execution is triggered by sending a negative (bit 7 set) high address; execution starts at address XADR ($0083). ...

  • Page 177

    RESET RUN 100kΩ 1kΩ 1.0µF 1N914 Red LED 470Ω 0.01µF 470Ω Green LED Erase check Green — EPROM erased Red — EPROM not erased Serial boot Green — programming OK Red — programming error 9600 BD 22µF +5V 8-bit + ...

  • Page 178

    Figure C-8 RAM parallel bootstrap schematic diagram Freescale C-16 RESET RUN 100kΩ 1kΩ 1N914 1.0µF + 0.01µF +5V + 100kΩ VPP NC PGM VCC ...

  • Page 179

    C.5.5 Bootstrap loader timing diagrams t COOE Address t ADE t DHE Data t max (address to data delay) ADE t min (data hold time) DHA t (load cycle time) COOE t (programming cycle time) CDDE Figure C-9 EPROM parallel ...

  • Page 180

    Address PC5 out Data PC6 in PD4 14 Freescale C- ADR t DHR t max HI t max EXR t max (address to data delay; PC6=PC5) ADR t min (data hold time) DHR t (load ...

  • Page 181

    C.6 DC electrical characteristics Note: The complete table of DC electrical characteristics can be found in Section 11.2. The values contained in the following table should be used in conjunction with those quoted in that section. Table C-4 Additional DC ...

  • Page 182

    THIS PAGE LEFT BLANK INTENTIONALLY 14 Freescale C-20 MC68HC705B5 MC68HC05B6 Rev. 4.1 ...

  • Page 183

    MC68HC05B16 Maskset errata This errata section outlines the differences between previously available masksets (D20J, F62J and G28F) and all other masksets. Unless otherwise stated, the main body of Appendix D refers to all these other masksets with any differences being ...

  • Page 184

    IRQ pin D.2 Self-check routines The self-check routines for the MC68HC05B16 are identical to those of the MC68HC05B4 with the following exception. The count byte on the MC68HC05B16 can be any value up to 256 ...

  • Page 185

    EEPROM Charge pump VPP1 15120 bytes ROM RESET COP watchdog IRQ OSC2 Oscillator OSC1 ÷ ÷ M68HC05 VDD VSS PD0/AN0 PD1/AN1 PD2/AN2 PD3/AN3 8-bit PD4/AN4 A/D converter PD5/AN5 PD6/AN6 PD7/AN7 VRH VRL Figure D-1 MC68HC05B16 block ...

  • Page 186

    D.3 External clock When using an external clock the OSC1 and OSC2 pins should be driven in antiphase, as shown in Figure D-2. The t OXOV external clock input. The equivalent specification of the external clock source should be used ...

  • Page 187

    MC68HC05B16 $0000 I/O (32 bytes) $0020 Page 0 User ROM (48 bytes) $0050 RAM1 (176 bytes) $00C0 Stack $0100 Options register $0101 Unprotected (31 bytes) $0120 EEPROM (256 bytes) Protected (224 bytes) $0200 $0250 RAM11 (176 bytes) $0300 User ROM ...

  • Page 188

    Register name Port A data (PORTA) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC) EEPROM/ECLK control A/D data (ADDATA) A/D status/control ...

  • Page 189

    MC68HC705B16 To ensure correct operation of the MC68HC705B16 after power-on, the device must be reset a second time after power-on. This can be done in software using the MC68HC705B16 watchdog. The following software sub-routine should be used: RESET2 BSET The ...

  • Page 190

    E.1 Features • 15 kbytes EPROM • 352 bytes of RAM • 576 bytes bootstrap ROM • Simultaneous programming bytes of EPROM • Optional pull-down resistors available on all port B and port C pins • ...

  • Page 191

    MC68HC705B16 $0000 I/O (32 bytes) $0020 Page 0 User EPROM (48 bytes) $0050 RAM1 (176 bytes) $00C0 Stack $0100 Options register $0101 Unprotected (31 bytes) $0120 EEPROM (256 bytes) Protected (224 bytes) $0200 Bootstrap ROM1 (80 bytes) $0250 RAM11 (176 ...

  • Page 192

    Register name Port A data (PORTA) Port B data (PORTB) Port C data (PORTC) Port D data (PORTD) Port A data direction (DDRA) Port B data direction (DDRB) Port C data direction (DDRC) EPROM/EEPROM/ECLK control A/D data (ADDATA) A/D status/control ...

  • Page 193

    E.2 External clock When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see Figure D-2). The OXOV ILCH external clock input. The equivalent specification of the external clock source should be ...

  • Page 194

    EPROM will not be available for code execution while the E6LAT bit is set. The V must occur externally after the E6PGM bit is set, for example under control of a signal generated on a pin by the programming routine. ...

  • Page 195

    ECLK See Section 4.3. E1ERA — EEPROM erase/programming bit Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the EEPROM is for erasing or programming purposes. 1 (set) – An erase operation ...

  • Page 196

    E.3.4 Mask option register Mask option register (MOR) (1) This register is implemented in EPROM; therefore reset has no effect on the individual bits. RTIM — Reset time This bit can modify the time t 1 (set) – ...

  • Page 197

    E.3.5 EEPROM options register (OPTR) Address (1) Options (OPTR) $0100 (1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits. EE1P – EEPROM protect bit In order to achieve a higher degree of protection, ...

  • Page 198

    E.4 Bootstrap mode The 432 bytes of self-check firmware on the MC68HC05B6 are replaced by 576 bytes of bootstrap firmware. A detailed description of the modes of operation within bootstrap mode is given below. The bootstrap program in mask ROM ...

  • Page 199

    Reset IRQ at 9V? Y TCAP1 set? Y Bootstrap mode Y A PD4 set PD3 set? N Parallel E/EEPROM bootstrap Program EPROM; parallel load; green LED flashes Programming OK? N Red LED on Bad EPROM programming Figure E-3 ...

  • Page 200

    Parallel bootstrap RAM PD4 set? Y Load next RAM byte N RAM1 full? Y Execute RAM program at $0050 14 Freescale E-12 Y Red LED flashes N N Transmit last four programmed locations Receive address Receive four data Y Green ...