MC68HC705B16CFN

Manufacturer Part NumberMC68HC705B16CFN
DescriptionIC MCU 2.1MHZ 15K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705B16CFN datasheet
 


Specifications of MC68HC705B16CFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI
PeripheralsPOR, WDTNumber Of I /o32
Program Memory Size15KB (15K x 8)Program Memory TypeOTP
Eeprom Size256 x 8Ram Size352 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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9.2.3.2
Miscellaneous register
Address
Miscellaneous
$000C
Note:
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in
Section
INTP, INTN — External interrupt sensitivity options
These two bits allow the user to select which edge the IRQ pin is sensitive to as shown in
Table
9-3. Both bits can be written to only while the I-bit is set, and are cleared by power-on or
external reset. Therefore the device is initialised with negative edge and low level sensitivity.
INTP
0
0
1
1
INTE — External interrupt enable
1 (set)
External interrupt function (IRQ) enabled.
0 (clear) –
External interrupt function (IRQ) disabled.
The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,
thus enabling the external interrupt function.
Table 9-3
describes the various triggering options available for the IRQ pin, however it is important
to re-emphasize here that in order to avoid any conflict and spurious interrupt, it is only possible
to change the external interrupt options while the I-bit is set. Any attempt to change the external
interrupt option while the I-bit is clear will be unsuccessful. If an external interrupt is pending, it will
automatically be cleared when selecting a different interrupt option.
Note:
If the external interrupt function is disabled by the INTE bit and an external interrupt is
sensed by the edge detector circuitry, then the interrupt request is latched and the
interrupt stays pending until the INTE bit is set. The internal latch of the external
interrupt is cleared in the first part of the service routine (except for the low level
MC68HC05B6
Rev. 4.1
bit 7
bit 6
bit 5
bit 4
bit 3
POR
INTP
INTN
INTE
SFA
3.8.
Table 9-3 IRQ sensitivity
INTN
IRQ sensitivity
0
Negative edge and low level sensitive
1
Negative edge only
0
Positive edge only
1
Positive and negative edge sensitive
RESETS AND INTERRUPTS
State
bit 2
bit 1
bit 0
on reset
SFB
SM
WDOG ?001 000?
Freescale
9-9
9