MC68HC705B16CFN

Manufacturer Part NumberMC68HC705B16CFN
DescriptionIC MCU 2.1MHZ 15K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705B16CFN datasheet
 


Specifications of MC68HC705B16CFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI
PeripheralsPOR, WDTNumber Of I /o32
Program Memory Size15KB (15K x 8)Program Memory TypeOTP
Eeprom Size256 x 8Ram Size352 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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Half carry (H)
This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.
Interrupt (I)
When this bit is set all maskable interrupts are masked. If an interrupt occurs while this bit is set,
the interrupt is latched and remains pending until the interrupt bit is cleared.
Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was
negative.
Zero (Z)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero.
Carry/borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred
during the last arithmetic operation. This bit is also affected during bit test and branch instructions
and during shifts and rotates.
10.2
Instruction set
The MCU has a set of 62 basic instructions. They can be grouped into five different types as
follows:
– Register/memory
– Read/modify/write
– Branch
– Bit manipulation
– Control
The following paragraphs briefly explain each type. All the instructions within a given type are
presented in individual tables.
This MCU uses all the instructions available in the M146805 CMOS family plus one more: the
unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents
of the accumulator (A) and the index register (X). The high-order product is then stored in the index
register and the low-order product is stored in the accumulator. A detailed definition of the MUL
instruction is shown in
Table
10-1.
MC68HC05B6
CPU CORE AND INSTRUCTION SET
Rev. 4.1
10
Freescale
10-3