MC68HC705B16CFN

Manufacturer Part NumberMC68HC705B16CFN
DescriptionIC MCU 2.1MHZ 15K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705B16CFN datasheet
 


Specifications of MC68HC705B16CFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI
PeripheralsPOR, WDTNumber Of I /o32
Program Memory Size15KB (15K x 8)Program Memory TypeOTP
Eeprom Size256 x 8Ram Size352 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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10.2.1
Register/memory Instructions
Most of these instructions use two operands. The first operand is either the accumulator or the
index register. The second operand is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register
operand. Refer to
Table 10-2
10.2.2
Branch instructions
These instructions cause the program to branch if a particular condition is met; otherwise, no
operation is performed. Branch instructions are two-byte instructions. Refer to
10.2.3
Bit manipulation instructions
The MCU can set or clear any writable bit that resides in the first 256 bytes of the memory space
(page 0). All port data and data direction registers, timer and serial interface registers,
control/status registers and a portion of the on-chip RAM reside in page 0. An additional feature
allows the software to test and branch on the state of any bit within these locations. The bit set, bit
clear, bit test and branch functions are all implemented with single instructions. For the test and
branch instructions, the value of the bit tested is also placed in the carry bit of the condition code
register. Refer to
Table
10.2.4
Read/modify/write instructions
These instructions read a memory location or a register, modify or test its contents, and write the
10
modified value back to memory or to the register. The test for negative or zero (TST) instruction is
an exception to this sequence of reading, modifying and writing, since it does not modify the value.
Refer to
Table 10-5
for a complete list of read/modify/write instructions.
10.2.5
Control instructions
These instructions are register reference instructions and are used to control processor operation
during program execution. Refer to
10.2.6
Tables
Tables for all the instruction types listed above follow. In addition there is a complete alphabetical
listing of all the instructions (see
instruction set of the M68HC05 MCU family (see
Freescale
10-4
for a complete list of register/memory instructions.
10-4.
Table 10-6
for a complete list of control instructions.
Table 10-7
and
Table
Table
10-9).
CPU CORE AND INSTRUCTION SET
Table
10-3.
10-8), and an opcode map for the
MC68HC05B6
Rev. 4.1