MC68HC705B16CFN

Manufacturer Part NumberMC68HC705B16CFN
DescriptionIC MCU 2.1MHZ 15K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705B16CFN datasheet
 


Specifications of MC68HC705B16CFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI
PeripheralsPOR, WDTNumber Of I /o32
Program Memory Size15KB (15K x 8)Program Memory TypeOTP
Eeprom Size256 x 8Ram Size352 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
Page 121
122
Page 122
123
Page 123
124
Page 124
125
Page 125
126
Page 126
127
Page 127
128
Page 128
129
Page 129
130
Page 130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
Page 121/302

Download datasheet (4Mb)Embed
PrevNext
Operation
Description
Condition
codes
Source
Form
Table 10-2 Register/memory instructions
Function
Load A from memory
LDA
A6
Load X from memory
LDX
AE
Store A in memory
STA
Store X in memory
STX
Add memory to A
ADD
AB
Add memory and carry to A
ADC
A9
Subtract memory
SUB
A0
Subtract memory from A
SBC
A2
with borrow
AND memory with A
AND
A4
OR memory with A
ORA
AA
Exclusive OR memory with A
EOR
A8
Arithmetic compare A
CMP
A1
with memory
Arithmetic compare X
CPX
A3
with memory
Bit test memory with A
BIT
A5
(logical compare)
Jump unconditional
JMP
Jump to subroutine
JSR
MC68HC05B6
CPU CORE AND INSTRUCTION SET
Rev. 4.1
Table 10-1 MUL instruction
X:A ← X*A
Multiplies the eight bits in the index register by the eight
bits in the accumulator and places the 16-bit result in the
concatenated accumulator and index register.
H : Cleared
I : Not affected
N : Not affected
Z : Not affected
C : Cleared
MUL
Addressing mode
Cycles
Bytes
Inherent
11
1
Addressing modes
Immediate
Direct
Extended
2
2
B6
2
3
C6
3
4
F6
2
2
BE
2
3
CE
3
4
FE
B7
2
4
C7
3
5
F7
BF
2
4
CF
3
5
FF
2
2
BB
2
3
CB
3
4
FB
2
2
B9
2
3
C9
3
4
F9
2
2
B0
2
3
C0
3
4
F0
2
2
B2
2
3
C2
3
4
F2
2
2
B4
2
3
C4
3
4
F4
2
2
BA
2
3
CA
3
4
FA
2
2
B8
2
3
C8
3
4
F8
2
2
B1
2
3
C1
3
4
F1
2
2
B3
2
3
C3
3
4
F3
2
2
B5
2
3
C5
3
4
F5
BC
2
2
CC
3
3
FC
BD
2
5
CD
3
6
FD
Opcode
$42
Indexed
Indexed
Indexed
(no
(8-bit
(16-bit
offset)
offset)
offset)
1
3
E6
2
4
D6
3
5
1
3
EE
2
4
DE
3
5
1
4
E7
2
5
D7
3
6
1
4
EF
2
5
DF
3
6
1
3
EB
2
4
DB
3
5
1
3
E9
2
4
D9
3
5
1
3
E0
2
4
D0
3
5
1
3
E2
2
4
D2
3
5
1
3
E4
2
4
D4
3
5
1
3
EA
2
4
DA
3
5
1
3
E8
2
4
D8
3
5
1
3
E1
2
4
D1
3
5
1
3
E3
2
4
D3
3
5
1
3
E5
2
4
D5
3
5
1
2
EC
2
3
DC
3
4
1
5
ED
2
6
DD
3
7
Freescale
10-5
10