MC68HC705B16CFN

Manufacturer Part NumberMC68HC705B16CFN
DescriptionIC MCU 2.1MHZ 15K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705B16CFN datasheet
 

Specifications of MC68HC705B16CFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI
PeripheralsPOR, WDTNumber Of I /o32
Program Memory Size15KB (15K x 8)Program Memory TypeOTP
Eeprom Size256 x 8Ram Size352 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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4) The exchange of data continues until the MC68HC705B16 has sent the four
data bytes and the host has sent the 2 address data bytes and 4 data bytes.
5) If the data is different from $00 for EPROM or $FF for EEPROM, it is
programmed at the address provided, while the next address and bytes are
received and the previous data is echoed.
6) Loop to 1.
After reset, the MC68HC705B16 serial bootstrap routine will first echo two blocks of four bytes at
$00, as no data is programmed yet.
If the data received is $00 for EPROM locations or $FF for EEPROM locations, no programming
in the EPROM and EEPROM1 takes place, and the contents of the accessed location are returned
as a prompt. The entire EPROM/EEPROM memory can be read in this fashion (serial dump).
Warning: When using this function with a programmed device, the device must be placed into
RAM/EPROM/EEPROM serial bootstrap mode without EPROM erase check (PD4 = 1).
Serial RAM loading and execute can be accomplished in this mode. A RAM byte will be written if
the address sent by the host in the serial protocol points to the RAM.
RAM bytes $008B–$00E3 and $0250–$02ED are available for user test programs. A 10-byte stack
resides at the top of RAMI, allowing, for example, one interrupt and two sub-routine levels. The
RAM addresses between $0050 and $008A are used by the loader and are therefore not available
to the user during serial loading/executing.
If the SEC bit is at ‘1’, program execution is triggered by sending a negative (bit 7 set) high
address; execution starts at address XADR ($008B).
In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see
Table
E-5). This allows programmers to use their own service-routine addresses. Each
pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors,
because an explicit jump (JMP) opcode is needed to cause the desired jump to the user’s service
routine address.
14
Freescale
E-18
Table E-5 Bootstrap vector targets in RAM
Vector targets in RAM
SCI interrupt
$02EE
Timer overflow
$02F1
Timer output compare
$02F4
Timer input capture
$02F7
IRQ
$02FA
SWI
$02FD
MC68HC705B16
MC68HC05B6
Rev. 4.1