MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 207

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
E.4.4
RAM parallel bootstrap
The program first checks the state of the security bit. If the SEC bit is active, i.e. ‘0’, the program
will not enter the RAM bootstrap mode and the red LED will flash. Otherwise the RAM bootstrap
program will start loading the RAM with external data (e.g. from a 2564 or 2764 EPROM). Before
loading a new byte the state of the PD4/AN4 pin is checked. If this pin goes to level ‘0’, or if the
RAM is full, then control is given to the loaded program at address $0050. See
Figure
E-4.
If the data is supplied by a parallel interface, handshaking will be provided by PC5 and PC6
according to
Figure
E-9. If the data comes from an external EPROM, the handshake can be
disabled by connecting together PC5 and PC6.
Figure E-10
provides a schematic diagram of a circuit that can be used to load the RAM with short
test programs. Up to 8 programs can be loaded in turn from the EPROM. Selection is
accomplished by means of the switches connected to the EPROM higher address lines (A8
through A10). If the user program sets PC0 to level ‘1’, this will disable the external EPROM, thus
rendering both port A output and port B input available. The EPROM parallel bootstrap loader
schematic can also be used
(Figure
lines will be at zero. The LEDs will stay off.
Address
PC5 out
Data
PC6 in
PD4
t
max (address to data delay; PC6=PC5)
ADR
t
min (data hold time)
DHR
t
(load cycle time; PC6=PC5)
CR
t
(PC5 handshake out delay)
HO
t
max (PC6 handshake in, data hold time)
HI
t
max (max delay for transition to be recognised during this cycle; PC6=PC5
EXR
Figure E-9 Parallel RAM loader timing diagram
MC68HC05B6
Rev. 4.1
E-7), provided VPP is at V
level. The high order address
DD
t
CR
t
HO
t
ADR
t
DHR
t
max
HI
t
max
EXR
1 machine cycle = 1/(2f
(Xtal))
0
MC68HC705B16
Figure E-3
and
16 machine cycles
4 machine cycles
49 machine cycles
5 machine cycles
10 machine cycles
30 machine cycles
14
Freescale
E-19

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