MC68HC705B16CFN

Manufacturer Part NumberMC68HC705B16CFN
DescriptionIC MCU 2.1MHZ 15K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705B16CFN datasheet
 


Specifications of MC68HC705B16CFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI
PeripheralsPOR, WDTNumber Of I /o32
Program Memory Size15KB (15K x 8)Program Memory TypeOTP
Eeprom Size256 x 8Ram Size352 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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Table H-8 DC electrical characteristics for 3.3V operation
= 3.3Vdc ± 10%, V
(V
= 0Vdc, T
DD
SS
(1)
Characteristic
Output voltage
= – 10 µA
I
LOAD
= +10 µA
I
LOAD
Output high voltage (I
= 0.8mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2
Output high voltage (I
= 1.6mA)
LOAD
TDO, SCLK, PLMA, PLMB
Output low voltage (I
= 1.6mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
TDO, SCLK, PLMA, PLMB
Output low voltage (I
= 1.6mA)
LOAD
RESET
Input high voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1,
IRQ, RESET, TCAP1, TCAP2, RDI
Input low voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ
RESET, TCAP1, TCAP2, RDI
(3)
Supply current
(For Guidance Only)
RUN (SM = 0) (See
Figure
11-1)
RUN (SM = 1) (See
Figure
11-2)
WAIT (SM = 0) (See
Figure
11-3)
WAIT (SM = 1) (See
Figure
11-4)
STOP
0 to 70 (standard)
– 40 to 85 (extended)
High-Z leakage current
PA0–7, PB0–7, PC0–7, TDO, RESET, SCLK
Input current (0 to 70)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
Input current (– 40 to 125)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
Capacitance
Ports (as input or output), RESET, TDO,
SCLK
IRQ, TCAP1, TCAP2, OSC1, RDI
PD0/AN0–PD7/AN7 (A/D off)
PD0/AN0–PD7/AN7 (A/D on)
(1) All I
measurements taken with suitable decoupling capacitors across the power supply to suppress the
DD
transient switching currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3) RUN and WAIT I
: measured using an external square-wave clock source (f
DD
0.2 V from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).
STOP /WAIT I
: all ports configured as inputs; V
DD
OSC1 = V
.
DD
WAIT I
is affected linearly by the OSC2 capacitance.
DD
MC68HC05B6
Rev. 4.1
= –40 to +85°C)
A
Symbol
Min
Typ
V
V
– 0.1
OH
DD
V
OL
V
V
– 0.3
V
OH
DD
DD
V
V
– 0.3
V
OH
DD
DD
V
0.1
OL
V
0.2
OL
V
0.7V
IH
DD
V
V
,
IL
SS
I
3
DD
I
1
DD
I
1.5
DD
I
0.5
DD
I
10
DD
I
10
DD
±0.2
I
IL
±0.2
I
IN
I
IN
C
OUT
C
OUT
C
12
IN
C
22
IN
OSC
= 0.2 V and V
= V
– 0.2 V: STOP I
IL
IH
DD
MC68HC705B32
(2)
Max
Unit
V
0.1
– 0.1
V
– 0.1
0.3
V
0.6
V
V
DD
0.2V
V
DD
TBD
mA
TBD
mA
TBD
mA
TBD
mA
TBD
µA
µA
TBD
±1
µA
±1
µA
±5
µA
12
pF
8
pF
pF
pF
= 2.0 MHz); all inputs
measured with
DD
Freescale
H-25
14