MC68HC705B16CFN

Manufacturer Part NumberMC68HC705B16CFN
DescriptionIC MCU 2.1MHZ 15K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705B16CFN datasheet
 


Specifications of MC68HC705B16CFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI
PeripheralsPOR, WDTNumber Of I /o32
Program Memory Size15KB (15K x 8)Program Memory TypeOTP
Eeprom Size256 x 8Ram Size352 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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3.8
Miscellaneous register
Address
Miscellaneous
$000C POR
(1) The POR bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
POR — Power-on reset bit (see
This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the
user to make a software distinction between a power-on and an external reset. This bit cannot be
set by software and is cleared by writing it to zero.
1 (set)
A power-on reset has occurred.
0 (clear) –
No power-on reset has occurred.
INTP, INTN — External interrupt sensitivity options (see
These two bits allow the user to select which edge the IRQ pin will be sensitive to (see
Both bits can be written to only while the I-bit is set, and are cleared by power-on or external reset,
thus the device is initialised with negative edge and low level sensitivity.
INTP
0
0
1
1
INTE — External interrupt enable (see
1 (set)
External interrupt function (IRQ) enabled.
0 (clear) –
External interrupt function (IRQ) disabled.
The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,
thus enabling the external interrupt function.
MC68HC05B6
Rev. 4.1
bit 7
bit 6
bit 5
bit 4
bit 3
(1)
INTP
INTN
INTE
SFA
Section
9.1)
Section
Table 3-3 IRQ sensitivity
INTN
IRQ sensitivity
0
Negative edge and low level sensitive
1
Negative edge only
0
Positive edge only
1
Positive and negative edge sensitive
Section
9.2)
MEMORY AND REGISTERS
State
bit 2
bit 1
bit 0
on reset
(2)
SFB
SM WDOG
?001 000?
9.2)
Table
3-3).
Freescale
3-9
3