MC68HC705B16CFN

Manufacturer Part NumberMC68HC705B16CFN
DescriptionIC MCU 2.1MHZ 15K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705B16CFN datasheet
 


Specifications of MC68HC705B16CFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI
PeripheralsPOR, WDTNumber Of I /o32
Program Memory Size15KB (15K x 8)Program Memory TypeOTP
Eeprom Size256 x 8Ram Size352 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $0000) produced
the framing error, the start bit will not be artificially induced and the receiver must actually detect
a logic one before the start bit can be recognised (see
Data
RDI
Data
6
RDI
Figure 6-6 Artificial start following a framing error
Expected stop
Break
RDI
6.9
Transmit data out (TDO)
Transmit data is the serial data from the internal data bus that is applied through the SCI to the
output line. Data format is as discussed in
generates a bit time by using a derivative of the RT clock, thus producing a transmission rate equal
to 1/16th that of the receiver sample clock (assuming the same baud rate is selected for both the
receiver and transmitter).
Freescale
6-8
Figure
Expected stop
Artificial edge
Data samples
a) Case 1: receive line low during artificial edge
Expected stop
Start edge
Data samples
b) Case 2: receive line high during expected start edge
Start
qualifiers
Data samples
Figure 6-7 SCI start bit following a break
Section 6.5
and shown in
SERIAL COMMUNICATIONS INTERFACE
6-7).
Data
Start bit
Data
Start bit
Detected as valid start edge
Start bit
Start edge
verification
samples
Figure
6-3. The transmitter
MC68HC05B6
Rev. 4.1