MC68HC705B16CFN Freescale Semiconductor, MC68HC705B16CFN Datasheet - Page 83

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MC68HC705B16CFN

Manufacturer Part Number
MC68HC705B16CFN
Description
IC MCU 2.1MHZ 15K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705B16CFN

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
15KB (15K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
352 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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R8 — Receive data bit 8
This read-only bit is the ninth serial data bit received when the SCI system is configured for nine
data bit operation (M = 1). The most significant bit (bit 8) of the received character is transferred
into this bit at the same time as the remaining eight bits (bits 0–7) are transferred from the serial
receive shifter to the SCI receive data register.
T8 — Transmit data bit 8
This read/write bit is the ninth data bit to be transmitted when the SCI system is configured for nine
data bit operation (M = 1). When the eight low order bits (bits 0–7) of a transmit character are
transferred from the SCI data register to the serial transmit shift register, this bit (bit 8) is
transferred to the ninth bit position of the shifter.
M — Mode (select character format)
The read/write M-bit controls the character length for both the transmitter and receiver at the same
time. The 9th data bit is most commonly used as an extra stop bit or it can also be used as a parity
bit (see
WAKE — Wake-up mode select
This bit allows the user to select the method for receiver wake-up. The WAKE bit can be read or
written to any time. See
MC68HC05B6
Rev. 4.1
1 (set)
0 (clear) –
1 (set)
0 (clear) –
Table
x = Don’t care
WAKE
6-1).
0
1
1
Start bit, 9 data bits, 1 stop bit.
Start bit, 8 data bits, 1 stop bit.
Wake-up on address mark; if RWU is set, SCI will wake-up if the 8th
(if M=0) or 9th (if M=1) bit received on the Rx line is set.
Wake-up on idle line; if RWU is set, SCI will wake-up after 11 (if M=0)
or 12 (if M=1) consecutive ‘1’s on the Rx line.
M
x
0
1
Table
SERIAL COMMUNICATIONS INTERFACE
Detection of an idle line allows the next data type received to cause the receive
data register to fill and produce an RDRF flag.
Detection of a received one in the eighth data bit allows an RDRF flag and
associated error flags.
Detection of a received one in the ninth data bit allows an RDRF flag and
associated error flags.
Table 6-1 Method of receiver wake-up
6-1.
Method of receiver wake-up
Freescale
6-11
6

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