MC68HC705B16CFN

Manufacturer Part NumberMC68HC705B16CFN
DescriptionIC MCU 2.1MHZ 15K OTP 52-PLCC
ManufacturerFreescale Semiconductor
SeriesHC05
MC68HC705B16CFN datasheet
 


Specifications of MC68HC705B16CFN

Core ProcessorHC05Core Size8-Bit
Speed2.1MHzConnectivitySCI
PeripheralsPOR, WDTNumber Of I /o32
Program Memory Size15KB (15K x 8)Program Memory TypeOTP
Eeprom Size256 x 8Ram Size352 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case52-PLCCLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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The D/A converter has two data registers associated with it, PLMA and PLMB.
Pulse length modulation A (PLMA)
Pulse length modulation B (PLMB)
This is a dual 8-bit resolution D/A converter associated with two output pins (PLMA and PLMB).
The outputs are pulse length modulated signals whose duty cycle ratio may be modified. These
signals can be used directly as PLMs, or the filtered average may be used as general purpose
analog outputs.
The longest repetition period is 4096 times the programmable timer clock period (CPU clock
multiplied by four), and the shortest repetition period is 256 times the programmable timer clock
period (the repetition rate frequencies for a 4 MHz crystal are 122 Hz and 1953 Hz respectively).
Registers PLMA ($0A) and PLMB ($0B) are associated with the pulse length values of the two
counters. A value of $00 loaded into these registers results in a continuously low output on the
corresponding D/A output pin. A value of $80 results in a 50% duty cycle output, and so on, to the
maximum value $FF corresponding to an output which is at ‘1’ for 255/256 of the cycle. When the
7
MCU makes a write to register PLMA or PLMB the new value will only be picked up by the D/A
converters at the end of a complete cycle of conversion. This results in a monotonic change of the
DC component at the output without overshoots or vicious starts (a vicious start is an output which
gives totally erroneous PLM during the period immediately following an update of the PLM D/A
registers). This feature is achieved by double buffering of the PLM D/A registers. Examples of
PWM output waveforms are shown in
$00
$01
T
$80
$FF
T = 4 CPU clocks in fast mode and 64 CPU clocks in slow mode
Freescale
7-2
Address
bit 7
bit 6
bit 5
bit 4
$000A
$000B
Figure
7-2.
256 T
255 T
128 T
255 T
Figure 7-2 PLM output waveform examples
PULSE LENGTH D/A CONVERTERS
State
bit 3
bit 2
bit 1
bit 0
on reset
0000 0000
0000 0000
128 T
T
MC68HC05B6
Rev. 4.1