MC68HC908JK3CDW Freescale Semiconductor, MC68HC908JK3CDW Datasheet
MC68HC908JK3CDW
Specifications of MC68HC908JK3CDW
Related parts for MC68HC908JK3CDW
MC68HC908JK3CDW Summary of contents
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MC68HC908JK1 MC68HRC908JK1 MC68HC908JK3 JC68HRC908JK3 MC68HC908JL3 MC68HRC908JL3 Technical Data M68HC08 Microcontrollers Rev. 1.1 MC68HC908JL3/H August 1, 2005 freescale.com ...
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... Section 15. Computer Operating Properly (COP 173 Section 16. Low Voltage Inhibit (LVI 179 Section 17. Break Module (BREAK 183 Section 18. Electrical Specifications 191 Section 19. Mechanical Specifications . . . . . . . . . . . . . 203 Section 20. Ordering Information . . . . . . . . . . . . . . . . . 207 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor List of Sections List of Sections Technical Data 3 ...
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... List of Sections Technical Data 4 MC68H(R)C908JL3 List of Sections Rev. 1.1 — Freescale Semiconductor ...
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... MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Section 2. Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Section 3. Random-Access Memory (RAM) Contents ...
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... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Arithmetic/Logic Unit (ALU Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table of Contents MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Section 7. System Integration Module (SIM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 75 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 75 Reset and System Initialization External Pin Reset ...
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... Oscillator During Break Mode 100 Section 9. Monitor ROM (MON) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table of Contents MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... TIM Counter Modulo Registers (TMODH:TMODL 130 10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1) . 131 10.10.5 TIM Channel Registers (TCH0H/L:TCH1H/ 135 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Security 113 Section 10. Timer Interface Module (TIM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Features ...
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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Port 148 Port A Data Register (PTA 149 Data Direction Register A (DDRA 150 Port A Input Pull-up Enable Register (PTAPUE 151 Port 153 Port B Data Register (PTB 153 Data Direction Register B (DDRB 153 Table of Contents MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Port 155 Port D Data Register (PTD 155 Data Direction Register D (DDRD 156 Port D Control Register (PDCR 157 Section 13. External Interrupt (IRQ) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 IRQ1 Pin ...
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... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 LVI Control Register (CONFIG2/CONFIG1 180 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 Section 17. Break Module (BREAK) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Table of Contents MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 18.13 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 18.14 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 186 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .186 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 186 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 186 Break Module Registers ...
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... Technical Data 14 Section 19. Mechanical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 20-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 20-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 28-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 28-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Section 20. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Table of Contents MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Title MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MCU Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Memory Map Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .30 FLASH Control Register (FLCR FLASH Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . 45 FLASH Block Protect Register (FLBPR Configuration Register 2 (CONFIG2 Configuration Register 1 (CONFIG1) ...
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... RC Oscillator External Connections . . . . . . . . . . . . . . . . . . . . .97 Monitor Mode Circuit 103 Low-Voltage Monitor Mode Entry Flowchart 106 Monitor Data Format 108 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Break Transaction .109 Monitor Mode Entry Timing .113 List of Figures Page MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... Configuration Register 2 (CONFIG2 180 16-3 Configuration Register 1 (CONFIG1 181 17-1 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 185 17-2 Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 185 17-3 Break Status and Control Register (BRKSCR 187 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Title List of Figures List of Figures Page Technical Data 17 ...
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... Typical Stop Mode IDD, with all Modules Disabled (25 ° 200 19-1 20-Pin PDIP (Case #738 204 19-2 20-Pin SOIC (Case #751D 204 19-3 28-Pin PDIP (Case #710 205 19-4 28-Pin SOIC (Case #751F .205 Technical Data 18 Title MC68H(R)C908JL3 List of Figures Page Rev. 1.1 — Freescale Semiconductor ...
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... Prescaler Selection 129 10-3 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . . 134 11-1 MUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Title Summary of Device Variations . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Signal Name Conventions ...
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... Oscillator Component Specifications (5V 196 18-7 DC Electrical Characteristics (3V 197 18-8 Control Timing (3V 198 18-9 Oscillator Component Specifications (3V 199 18-10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 18-11 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 20-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Technical Data 20 Title MC68H(R)C908JL3 List of Tables Page Rev. 1.1 — Freescale Semiconductor ...
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... All references to the MC68H(R)C908JL3 in this data book apply equally to the MC68H(R)C908JK3 and MC68H(R)C908JK1, unless otherwise stated. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table 1-1 ...
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... I/O with pull-up – 2 ICAP/OCAP/PWM 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 22 1 (with RC oscillator option selected) General Description MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... MCU Block Diagram Figure 1-1 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor System protection features: – Optional computer operating properly (COP) reset – Optional low-voltage detection with reset and selectable trip points for 3V and 5V operation. – Illegal opcode detection with reset – ...
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PTD[0:7] PTD DDRD CPU CONTROL CPU REGISTERS ADC[0:7]/ PTB[0:7] ADC[11:8]/ COND CODE REG PTD[0:3] 128 BYTES RAM RST, IRQ1: PIN HAS INTERNAL 30K PULL-UP PTD[6:7]: PINS HAVE 25mA OPEN-DRAIN OUTPUT & PROGRAMMABLE 5K PULL-UP PTA[0:5], PTD[2:3], PTD[6:7]: PIN HAS LED ...
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... Pin Assignments The MC68H(R)C908JL3 is available in 28-pin packages and the MC68H(R)C908JK3/JK1 in 20-pin packages. assignment for the two packages. OSC2/PTA6 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor 28 1 IRQ1 RST 27 PTA0 2 PTA5 26 VSS 3 PTD4 25 OSC1 4 PTD5 24 5 PTD2 23 PTA1 6 PTA4 22 VDD 7 PTD3 8 21 ...
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... Table 1-2. Pin Functions IN/OUT In/Out In/Out In/Out In/Out In/Out In/Out General Description Table 1-2. VOLTAGE LEVEL Out 0V Input VDD VDD to VDD+V Input HI In Analog Out Analog VDD VDD In VDD In VDD VDD In Analog VDD Input Analog VDD VDD MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... The CPU08 can address 64 Kbytes of memory space. The memory map, shown in • • • • MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Figure 2-1, includes: 4096 bytes of user FLASH for MC68H(R)C908JL3/JK3 1536 bytes of user FLASH for MC68H(R)C908JK1 128 bytes of RAM ...
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... MONITOR ROM ↓ 448 BYTES $FFCF $FFD0 USER VECTORS ↓ 48 BYTES $FFFF Technical Data 28 RAM Figure 2-1. Memory Map Memory $0100 UNIMPLEMENTED ↓ 62720 BYTES $F5FF FLASH MEMORY $F600 ↓ MC68H(R)C908JK1 1536 BYTES $FBFF MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... ROM addresses that contain the instructions for the monitor functions. (See MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor $FE00 (Break Status Register, BSR) $FE01 (Reset Status Register, RSR) $FE02 (Reserved, SUBAR) $FE03 (Break Flag Control Register, BFCR) $FE04 (Interrupt Status Register 1, INT1) ...
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... DDRD6 DDRD5 DDRD4 Unimplemented Memory Bit 0 PTA3 PTA2 PTA1 PTA0 PTB3 PTB2 PTB1 PTB0 PTD3 PTD2 PTD1 PTD0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 DDRD3 DDRD2 DDRD1 DDRD0 SLOWD7 SLOWD6 PTDPU7 PTDPU6 Reserved MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... One-time writable register after each reset. * LVIT1 and LVIT0 reset to logic power-on reset (POR) only. Read: TIM Status and Control $0020 Register Write: (TSC) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Bit PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 ...
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... Bit1 Bit0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 CH0MAX ELS0B ELS0A TOV0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS1B ELS1A TOV1 CH1MAX Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 R = Reserved MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... Read: Break Flag Control $FE03 Register Write: (BFCR) Reset: Read: Interrupt Status Register 1 $FE04 Write: (INT1) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Bit COCO AIEN ADCO CH4 AD7 AD6 AD5 AD4 Indeterminate after reset ...
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... BRKE BRKA Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented Memory Bit IF15 HVEN MASS ERASE PGM BPR3 BPR2 BPR1 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 Reserved MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... Vector Priority MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Table 2-1. Vector Addresses Vector Address Lowest $FFDE IF15 $FFDF $FFE0 IF14 $FFE1 IF13 to — IF6 $FFF2 IF5 $FFF3 $FFF4 IF4 $FFF5 $FFF6 IF3 $FFF7 IF2 — $FFFA IF1 $FFFB $FFFC — $FFFD $FFFE — ...
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... Memory Technical Data 36 MC68H(R)C908JL3 Memory Freescale Semiconductor Rev. 1.1 — ...
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... Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE: For M6805 compatibility, the H register is not stacked. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Random-Access Memory (RAM) Technical Data 37 ...
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... The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Technical Data 38 Random-Access Memory (RAM) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... MC68H(R)C908JL3/JK3: 4096 bytes user FLASH from $EC00 – $FBFF. MC68H(R)C908JK1: 1536 bytes user FLASH from $F600 – $FBFF. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Section 4. FLASH Memory (FLASH) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 FLASH Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 41 FLASH Mass Erase Operation ...
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... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 40 $FE08 Bit Figure 4-1. FLASH Control Register (FLCR) FLASH Memory (FLASH Bit 0 HVEN MASS ERASE PGM MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... Write any data to any FLASH location within the address range of 3. Wait for a time Set the HVEN bit. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor 1 = High voltage enabled to array and charge pump High voltage disabled to array and charge pump off 1 = Mass Erase operation selected 0 = Block Erase operation selected 1 = Erase operation selected ...
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... Technical Data 42 (1ms). ERASE (5µs). nvh (1µs) the memory can be accessed in read mode rcv , (10µs). nvs (4ms). ERASE (100µs). nvh1 (1µs) the memory can be accessed in read mode rcv , FLASH Memory (FLASH) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... Clear the HVEN bit. 12. After time, t This program sequence is repeated throughout the memory until all data is programmed. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor shows a flowchart of the programming algorithm.) operation and enables the latching of address and data for programming. the row to be programmed. (10µs). nvs (5µ ...
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... FLASH memory which protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations. Technical Data 44 max. FLASH Memory (FLASH) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... PROG This row program algorithm assumes the row programmed are initially erased. Figure 4-2. FLASH Programming Flowchart MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor 1 Set PGM bit 2 Write any data to any FLASH address within the row address range desired 3 Wait for a time, t ...
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... The entire FLASH memory is not protected. FLASH Memory (FLASH Bit 0 0 BPR3 BPR2 BPR1 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor FLASH Memory (FLASH) FLASH Memory (FLASH) Technical Data 47 ...
Page 48
... FLASH Memory (FLASH) Technical Data 48 FLASH Memory (FLASH) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 49
... CONFIG2). The configuration registers enables or disables the following options: • • • • • • MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Stop mode recovery time (32 × 2OSCOUT cycles or 4096 × 2OSCOUT cycles) STOP instruction Computer operating properly module (COP) COP reset period (COPRS × 2OSCOUT – ...
Page 50
... LVIT1, LVIT0 — Low Voltage Inhibit trip voltage selection bits Detail description of the LVI control signals is given in Technical Data 48 Figure 5-1 and Figure $001E Bit IRQPUD R R LVIT1 Not affected Not affected Reserved Figure 5-1. Configuration Register 2 (CONFIG2) Configuration Register (CONFIG) 5- Bit 0 LVIT0 Section 16. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 51
... Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal, do not set the SSREC bit. STOP enables the STOP instruction. COPD — COP Disable Bit COPD disables the COP module. (See Operating Properly MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor $001F Bit COPRS ...
Page 52
... Configuration Register (CONFIG) Technical Data 50 Configuration Register (CONFIG) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 53
... M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Section 6. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Stack Pointer ...
Page 54
... Kbytes • Low-power stop and wait modes 6.4 CPU Registers Figure 6-1 the memory map. Technical Data 52 shows the five CPU registers. CPU registers are not part of Central Processor Unit (CPU) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 55
... Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: Write: Reset: MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Figure 6-1. CPU Registers Bit Unaffected by reset Figure 6-2. Accumulator (A) Central Processor Unit (CPU) ...
Page 56
... The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Technical Data 54 Bit Indeterminate Figure 6-3. Index Register (H:X) Central Processor Unit (CPU) Bit MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 57
... Read: Write: Reset: 6.4.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Bit ...
Page 58
... The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor Carry between bits 3 and carry between bits 3 and 4 Technical Data 56 Bit Indeterminate Figure 6-6. Condition Code Register (CCR) Central Processor Unit (CPU Bit MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 59
... Z — Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor 1 = Interrupts disabled 0 = Interrupts enabled 1 = Negative result 0 = Non-negative result 1 = Zero result 0 = Non-zero result Central Processor Unit (CPU) ...
Page 60
... Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock Technical Data 58 Central Processor Unit (CPU) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 61
... Opcode Map See MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock ...
Page 62
... EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 63
... Branch if Interrupt Mask Set BNE rel Branch if Not Equal BPL rel Branch if Plus BRA rel Branch Always MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Table 6-1. Instruction Set Summary Description PC ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? (N ⊕ ← (PC rel ? ( ⊕ ← (PC rel ? ( ← (PC rel ? ( ← ...
Page 64
... DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR IMM IMM IX1 IX SP1 9E61 DIR INH 4F 1 INH 5F 1 INH 8C 1 IX1 SP1 9E6F ff 4 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 65
... Decrement DEC opr,X DEC ,X DEC opr,SP DIV Divide MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Table 6-1. Instruction Set Summary Description (A) – (M) M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) M ← ...
Page 66
... FD 4 IMM DIR EXT IX2 – IX1 SP1 9EE6 ff 4 SP2 9ED6 IMM – DIR IMM DIR EXT IX2 – IX1 SP1 9EEE ff 4 SP2 9EDE DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 67
... PULX Pull X from Stack ROL opr ROLA ROLX Rotate Left through Carry ROL opr,X ROL ,X ROL opr,SP MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Table 6-1. Instruction Set Summary Description ← (M) (M) Destination Source H:X ← (H: (IX+D, DIX+) X:A ← (X) × (A) M ← –(M) = $00 – (M) A ← ...
Page 68
... SP1 9E66 INH IMM DIR EXT IX2 IX1 SP1 9EE2 ff 4 SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 69
... Transfer SP to H:X TXA Transfer TXS Transfer H MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Table 6-1. Instruction Set Summary Description A ← (A) – (M) PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← ...
Page 70
... Zero bit & Logical AND | Logical OR ⊕ Logical EXCLUSIVE Contents of –( ) Negation (two’s complement) # Immediate value « Sign extend ← Loaded with ? If : Concatenated with Set or cleared — Not affected Central Processor Unit (CPU) CCR MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 71
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR 1 INH ...
Page 72
... Central Processor Unit (CPU) Technical Data 70 Central Processor Unit (CPU) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 73
... MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 75 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 75 Reset and System Initialization External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 77 Power-On Reset ...
Page 74
... Technical Data 72 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Break Status Register (BSR .91 Reset Status Register (RSR Break Flag Control Register (BFCR Figure 7-1. Figure 7 summary of the SIM I/O registers. System Integration Module (SIM) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 75
... Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor STOP/WAIT CONTROL SIM COUNTER ÷2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL MASTER RESET ...
Page 76
... Write: (INT3) Reset: Figure 7-2. SIM I/O Register Summary Technical Data 74 Bit POR PIN COP ILOP BCFE IF5 IF4 IF3 IF14 Unimplemented System Integration Module (SIM Bit 0 SBSW NOTE ILAD MODRST LVI IF1 IF15 Reserved MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 77
... Upon exit from stop mode by an interrupt, break, or reset, the SIM allows 2OSCOUT to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay time-out. This time-out is selectable as 4096 or 32 2OSCOUT cycles. (See MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor From 2OSCOUT SIM COUNTER OSCILLATOR OSCOUT ÷ ...
Page 78
... SIM Table 7-2 for details. Figure 7-4 Table 7-2. PIN Bit Set Timing Number of Cycles Required to Set PIN POR 4163 (4096 + System Integration Module (SIM) 7.5 SIM Counter), but an Registers.) shows the relative timing MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 79
... RST shown in Figure 2OSCOUT The COP reset is asynchronous to the bus clock. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Figure 7-4. External Reset Timing Figure 7-6 . Sources of Internal 7-5. IRST RST PULLED LOW BY MCU RST ...
Page 80
... The POR bit of the reset status register (RSR) is set and all other bits in the register are cleared. OSC1 PORRST 4096 CYCLES 2OSCOUT OSCOUT RST IAB Technical Data CYCLES CYCLES Figure 7-7. POR Recovery System Integration Module (SIM) $FFFE $FFFF MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 81
... MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor 12 4 – 2OSCOUT cycles, drives the COP counter. The COP + V while the MCU is in monitor mode. The COP module can be ...
Page 82
... External crystal applications should use the full stop recovery time, that is, with SSREC cleared in the configuration register (CONFIG). Technical Data 80 voltage falls to the LVI trip voltage V System Integration Module (SIM) . The LVI bit in the SIM TRIP MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 83
... Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) Reset Break interrupts ...
Page 84
... INTERRUPT? NO YES TIMER INTERRUPT? NO STACK CPU REGISTERS. LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES UNSTACK CPU REGISTERS. INSTRUCTION? NO EXECUTE INSTRUCTION. Figure 7-8. Interrupt Processing System Integration Module (SIM) SET I BIT. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 85
... When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrupt enable bit is MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Figure 7-9 shows interrupt recovery timing. SP – – – – ...
Page 86
... H register and then restore it prior to exiting the routine. Technical Data 84 CLI LDA #$FF INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Figure 7-11 Interrupt Recognition Example System Integration Module (SIM) Figure 7-11 BACKGROUND ROUTINE MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 87
... ADC Conversion Complete Interrupt Note: 1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Table 7-3 summarizes the interrupt sources and the interrupt Table 7-3. Interrupt Sources Flag Mask — ...
Page 88
... Technical Data 86 $FE04 Bit IF5 IF4 IF3 Reserved Figure 7-12. Interrupt Status Register 1 (INT1) Table 7-3. $FE05 Bit IF14 Reserved Figure 7-13. Interrupt Status Register 2 (INT2) Table 7-3. System Integration Module (SIM Bit 0 0 IF1 Bit MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 89
... Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor $FE06 Bit ...
Page 90
... Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the break Technical Data 88 Figure 7-15 shows the timing for wait mode entry. System Integration Module (SIM) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 91
... Figure 7-16 EXITSTOPWAIT NOTE: EXITSTOPWAIT = 2OSCOUT MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor IAB WAIT ADDR WAIT ADDR + 1 IDB PREVIOUS DATA NEXT OPCODE R/W NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction ...
Page 92
... NOTE: Previous data can be operand data or the STOP opcode, depending on the last Technical Data 90 Figure 7-18 shows stop mode entry timing. IAB STOP ADDR STOP ADDR + 1 IDB PREVIOUS DATA NEXT OPCODE instruction. Figure 7-18. Stop Mode Entry Timing System Integration Module (SIM) SAME SAME SAME SAME MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 93
... Break Status Register (BSR) The break status register contains a flag to indicate that a break caused an exit from stop or wait mode. Address: Read: Write: Reset: MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor STOP RECOVERY PERIOD STOP + 2 STOP + 2 STOP +1 Table 7-4. SIM Registers Address Register $FE00 BSR ...
Page 94
... POR bit and clears all other bits in the register. Technical Data 92 ; See if wait mode or stop mode was exited ; by break RETURNLO is not zero, ; then just decrement low byte. ; Else deal with high byte, too. ; Point to WAIT/STOP opcode. ; Restore H register. System Integration Module (SIM) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 95
... ILOP — Illegal Opcode Reset Bit ILAD — Illegal Address Reset Bit (opcode fetches only) MODRST — Monitor Mode Entry Module Reset bit LVI — Low Voltage Inhibit Reset bit MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor $FE01 Bit POR PIN COP ...
Page 96
... BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break Technical Data 94 $FE03 Reserved Figure 7-22. Break Flag Control Register (BFCR) System Integration Module (SIM Bit MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 97
... The oscillator module provides the reference clock for the MCU system and bus. Two types of oscillator modules are available: • • MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Section 8. Oscillator (OSC) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 X-tal Oscillator (MC68HC908xxx Oscillator (MC68HRC908xxx I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Crystal Amplifier Input Pin (OSC1 Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK) ...
Page 98
... B *R can be zero (shorted) when used with higher-frequency crystals. S Refer to manufacturer’s data See Section 18 Figure 8-1. X-tal Oscillator External Connections Oscillator (OSC) 8-1. This figure shows only To SIM OSCOUT ÷ 2 for component value requirements. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 99
... R and one C. Component values should have a tolerance less, to obtain a clock source with less than 10% tolerance. The oscillator configuration uses two components: • • From SIM MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ) is included in the diagram to follow strict Pierce S C EXT R EXT SIMOSCEN Ext-RC ...
Page 100
... X-tal oscillator Inverting OSC1 Controlled by PTAEN bit in PTAPUER ($0D) RC oscillator PTA6EN = 0: RCCLK output PTA6EN = 1: PTA6 I/O ) and comes directly from the crystal oscillator circuit. XCLK shows only the logical relation of XTALCLK to OSC1 and Oscillator (OSC) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 101
... The WAIT instruction has no effect on the oscillator logic. OSCOUT and 2OSCOUT continues to drive to the SIM module. 8.6.2 Stop Mode The STOP instruction disables the XTALCLK or the RCCLK output, hence OSCOUT and 2OSCOUT. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Oscillator (OSC) Oscillator (OSC) Figure 8-2 Technical Data 99 ...
Page 102
... Oscillator (OSC) 8.7 Oscillator During Break Mode The oscillator continues to drive OSCOUT and 2OSCOUT when the device enters the break state. Technical Data 100 MC68H(R)C908JL3 Oscillator (OSC) Rev. 1.1 — Freescale Semiconductor ...
Page 103
... Monitor mode entry can be achieved without use of the higher test voltage, V blank, thus reducing the hardware requirements for in-circuit programming. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Section 9. Monitor ROM (MON) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Data Format ...
Page 104
... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 102 1 Figure 9-1 shows a example circuit used to enter monitor Monitor ROM (MON reset vector applied DD HI MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 105
... Input clock = OSC1; Bus clock depends on SW1. SW2: Position D — Bus clock source = X-TAL or RC oscillator. Bus clock = XTALCLK ÷ RCCLK ÷ See Table 18-4 for IRQ1 voltage level requirements. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Figure 18-1 for component 10k Ω OSC1 OSC2 (SEE NOTE 4 AND ...
Page 106
... OSC1. 9600 baud communication on PTB0. COP disabled. Low-voltage entry to monitor mode. 9600 baud communication on PTB0. COP disabled. Enters User mode. If $FFFE and $FFFF is or blank, MCU will encounter an illegal address reset. for monitor mode entry. HI MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 107
... IRQ1 or the RST. Figure the reset vector is blank and IRQ1 = V (XTALCLK or RCCCLK) of 9.8304MHz is required for a baud rate of 9600. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor +V is applied to IRQ1 and PTB3 is low upon monitor mode entry HI condition set 1), the bus frequency is a divide-by-two of the (Table 9 applied to either the IRQ1 or the RST ...
Page 108
... Technical Data 106 POR RESET NO IS VECTOR BLANK? YES MONITOR MODE EXECUTE MONITOR CODE POR NO TRIGGERED? YES 9.5 Security.) After the security bytes, the MCU sends a Monitor ROM (MON) NORMAL USER MODE MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 109
... IRQ1 = V Blank reset vector, MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor is a summary of the vector differences between user mode Table 9-2. Monitor Mode Vector Differences Reset Reset COP Vector ...
Page 110
... Figure 9-5. Read Transaction Monitor ROM (MON) and Figure 9-4.) NEXT START STOP BIT 5 BIT 6 BIT 7 BIT BIT NEXT START BIT 5 BIT 6 BIT 7 STOP BIT BIT STOP NEXT BIT BIT 5 BIT 6 BIT 7 START BIT ADDR. LOW DATA RESULT MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 111
... Commands The monitor ROM uses the following commands: • • • • • • MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor MISSING STOP BIT Figure 9-6. Break Transaction READ (read memory) WRITE (write memory) ...
Page 112
... None Opcode $49 Command Sequence SENT TO MONITOR WRITE WRITE ADDR. HIGH ECHO Technical Data 110 ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. HIGH ADDR. LOW ADDR. LOW Monitor ROM (MON) ADDR. LOW DATA RESULT DATA DATA MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 113
... SENT TO MONITOR IWRITE IWRITE ECHO NOTE: A sequence of IREAD or IWRITE commands can sequentially access a block of memory over the full 64-Kbyte memory map. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor DATA DATA RESULT DATA DATA Monitor ROM (MON) Monitor ROM (MON) Technical Data 111 ...
Page 114
... READSP ECHO Table 9-9. RUN (Run User Program) Command Description Executes RTI instruction Operand None Data Returned None Opcode $28 Command Sequence SENT TO MONITOR RUN RUN ECHO Technical Data 112 SP HIGH SP LOW RESULT Monitor ROM (MON) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 115
... RST PTB0 NOTES Echo delay, 2 bit times 2 = Data return delay, 2 bit times 4 = Wait 1 bit time before sending next byte. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor 4096 + 32 OSCXCLK CYCLES 24 BUS CYCLES FROM HOST FROM MCU Figure 9-7. Monitor Mode Entry Timing Monitor ROM (MON) ...
Page 116
... FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). Technical Data 114 Monitor ROM (MON) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 117
... TIM Counter Modulo Registers (TMODH:TMODL 130 10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1) . 131 10.10.5 TIM Channel Registers (TCH0H/L:TCH1H/ 135 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Section 10. Timer Interface Module (TIM) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 TIM Counter Prescaler ...
Page 118
... TIM Generic Pin Names: Full TIM Pin Names: Technical Data 116 is a block diagram of the TIM. Table 10-1. The generic pin name appear in the Table 10-1. Pin Name Conventions TCH0 PTD4/TCH0 Timer Interface Module (TIM) TCH1 PTD5/TCH1 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 119
... COMPARATOR TMODH:TMODL CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor shows the structure of the TIM. The central component of PRESCALER SELECT PS2 PS1 PS0 ELS0B ELS0A CH0F MS0A MS0B ELS1B ELS1A ...
Page 120
... PS2 PS1 PS0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS0B ELS0A TOV0 CH0MAX Bit11 Bit10 Bit9 Bit8 Bit3 Bit2 Bit1 Bit0 ELS1B ELS1A TOV1 CH1MAX MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 121
... When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Read: Bit15 Bit14 Bit13 Write: Reset: ...
Page 122
... Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM Technical Data 120 10.5.3 Output Compare. The pulses are Timer Interface Module (TIM) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 123
... Program the TIM to set the pin if the state of the PWM pulse is logic zero. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor shows, the output compare value in the TIM channel Timer Interface Module (TIM) Timer Interface Module (TIM) Technical Data 121 ...
Page 124
... WIDTH OUTPUT COMPARE Figure 10-3. PWM Period and Pulse Width (see 10.10.1 TIM Status and Control Register 10.5.4 Pulse Width Modulation Timer Interface Module (TIM) OVERFLOW OUTPUT OUTPUT COMPARE COMPARE (TSC)). (PWM). The pulses are MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 125
... PWM function, and TIM channel 1 status and control register MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse ...
Page 126
... PWM signals) to the mode select bits, MSxB:MSxA. (See Table compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Timer Interface Module (TIM) 10-3.) Table 10-3.) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 127
... CPU interrupt request from the TIM can bring the MCU out of wait mode. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor TIM overflow flag (TOF) — The TOF bit is set when the TIM counter value rolls over to $0000 after matching the value in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests ...
Page 128
... Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTD4/TCH0 can be configured as a buffered output compare or buffered PWM pin. Technical Data 126 (See 7.8.3 Break Flag Control Register Timer Interface Module (TIM) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 129
... TOF is set and then writing a logic zero to TOF. If another TIM MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor TIM status and control register (TSC) TIM control registers (TCNTH:TCNTL) TIM counter modulo registers (TMODH:TMODL) TIM channel status and control registers (TSC0 and TSC1) ...
Page 130
... PS[2:0] — Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as PS[2:0] bits. Technical Data 128 Table 10-2 Timer Interface Module (TIM) shows. Reset clears the MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 131
... TIM counter registers. NOTE: If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Table 10-2. Prescaler Selection PS1 PS0 ...
Page 132
... TCNTH Bit Bit15 Bit14 Bit13 Bit12 $0022 TCNTL Bit Bit7 Bit6 Bit5 Bit4 Unimplemented Figure 10-5. TIM Counter Registers (TCNTH:TCNTL) Timer Interface Module (TIM Bit 0 Bit11 Bit10 Bit9 Bit8 Bit 0 Bit3 Bit2 Bit1 Bit0 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 133
... TIM Channel Status and Control Registers (TSC0:TSC1) Each of the TIM channel status and control registers does the following: • • • • • • • • MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor $0023 TMODH Bit Bit15 Bit14 Bit13 Bit12 $0024 ...
Page 134
... Channel x CPU interrupt requests disabled Technical Data 132 $0025 TSC0 Bit CH0F CH0IE MS0B MS0A $0028 TSC1 Bit CH1F 0 CH1IE MS1A Unimplemented Timer Interface Module (TIM Bit 0 ELS0B ELS0A TOV0 CH0MAX Bit 0 ELS1B ELS1A TOV1 CH1MAX MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 135
... I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 10-3 ELSxB and ELSxA bits. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled Table 10- Unbuffered output compare/PWM operation 0 = Input capture operation Table 10-3 ...
Page 136
... Pin under Port Control; Initial Output Level Low Capture on Rising Edge Only Capture on Falling Edge Only Capture on Rising or Falling Edge Toggle Output on Compare Clear Output on Compare Set Output on Compare Toggle Output on Compare Clear Output on Compare Set Output on Compare MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 137
... TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor OVERFLOW OVERFLOW PERIOD TCHx OUTPUT OUTPUT COMPARE COMPARE Figure 10-8 ...
Page 138
... Indeterminate after reset $02A TCH1L Bit Bit7 Bit6 Bit5 Bit4 Indeterminate after reset Timer Interface Module (TIM Bit 0 Bit11 Bit10 Bit9 Bit8 Bit 0 Bit3 Bit2 Bit1 Bit0 Bit 0 Bit11 Bit10 Bit9 Bit8 Bit 0 Bit3 Bit2 Bit1 Bit0 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 139
... Introduction This section describes the analog-to-digital converter (ADC). The ADC is an 8-bit, 12-channels analog-to-digital converter. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Continuous Conversion ...
Page 140
... ADC. Technical Data 138 Bit COCO AIEN ADCO CH4 AD7 AD6 AD5 AD4 Indeterminate after reset 0 ADIV2 ADIV1 ADIV0 Analog-to-Digital Converter (ADC Bit 0 CH3 CH2 CH1 CH0 AD3 AD2 AD1 AD0 Figure 11-2 shows a MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 141
... The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor DDRBx/DDRDx RESET PTBx/PTDx ADC DATA REGISTER ADC VOLTAGE IN ...
Page 142
... ADC status and control register or reading of the ADC data register. Technical Data 140 and $00 if less than ADC Clock Cycles Conversion Time = ADC Clock Frequency Analog-to-Digital Converter (ADC) , the ADC converts the DD the ADC SS, and V are MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 143
... ADC conversion after exiting stop mode. 11.7 I/O Signals The ADC module has 12 channels that are shared with I/O port B and port D. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Analog-to-Digital Converter (ADC) Analog-to-Digital Converter (ADC) Technical Data 141 ...
Page 144
... When the AIEN bit is a logic 1 (CPU interrupt enabled), the COCO is a read-only bit, and will always be logic 0 when read. Technical Data 142 $003C Bit COCO AIEN ADCO CH4 Unimplemented Analog-to-Digital Converter (ADC Bit 0 CH3 CH2 CH1 CH0 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 145
... MCU when the ADC is not used. Reset sets all of these bits to a logic 1. NOTE: Recovery from the disabled state requires one conversion cycle to stabilize. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor 1 = ADC interrupt enabled 0 = ADC interrupt disabled 1 = Continuous ADC conversion 0 = One ADC conversion Table 11-1.) Analog-to-Digital Converter (ADC) Analog-to-Digital Converter (ADC) ...
Page 146
... Analog-to-Digital Converter (ADC) Input Select PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 PTD3 PTD2 PTD1 PTD0 Unused — (see Note 1) — Reserved — Unused V (see Note 2) DDA V (see Note 2) SSA ADC power off MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 147
... ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. shows the available clock configurations. The ADC clock should be set to approximately 1MHz. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor $003D Bit AD7 ...
Page 148
... Table 11-2. ADC Clock Divide Ratio ADIV1 ADIV0 Analog-to-Digital Converter (ADC) ADC Clock Rate ADC Input Clock ÷ 1 ADC Input Clock ÷ 2 ADC Input Clock ÷ 4 ADC Input Clock ÷ 8 ADC Input Clock ÷ 16 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 149
... Although the I/O ports do not require termination for proper SS operation, termination reduces excess current consumption and the possibility of electrostatic damage. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Port 148 Port A Data Register (PTA 149 Data Direction Register A (DDRA 150 Port A Input Pull-up Enable Register (PTAPUE 151 Port 153 Port B Data Register (PTB) ...
Page 150
... I/O Ports Bit 0 PTA3 PTA2 PTA1 PTA0 PTB3 PTB2 PTB1 PTB0 PTD3 PTD2 PTD1 PTD0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 DDRD3 DDRD2 DDRD1 DDRD0 SLOWD7 SLOWD6 PTDPU7 PTDPU6 Section 14. Each port A MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 151
... A. Reset has no effect on port A data. KBI[6:0] — Port A Keyboard Interrupts The keyboard interrupt enable bits, KBIE6-KBIE0, in the keyboard interrupt control register (KBAIER) enable the port A pins as external interrupt pins, (see MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor $0000 Bit PTA6 ...
Page 152
... Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from Figure 12-4 Technical Data 150 $0004 Bit DDRA6 DDRA5 DDRA4 Figure 12-3. Data Direction Register A (DDRA) shows the port A I/O logic. I/O Ports Bit 0 DDRA3 DDRA2 DDRA1 DDRA0 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 153
... DDRAx be configured as input. Each pull-up device is automatically and dynamically disabled when its corresponding DDRAx bit is configured as output. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor READ DDRA ($0004) WRITE DDRA ($0004) DDRAx RESET WRITE PTA ($0000) PTAx READ PTA ($0000) Figure 12-4 ...
Page 154
... Table 12-1. Port A Pin Functions Accesses to DDRB I/O Pin Mode Read/Write (2) Input, V DDRA6-DDRA0 DD (4) Input, Hi-Z DDRA6-DDRA0 Output DDRA6-DDRA0 I/O Ports Bit 0 PTAPUE PTAPUE PTAPUE PTAPUE Accesses to PTB Read Write (3) Pin PTA6-PTA0 (3) Pin PTA6-PTA0 PTA6-PTA0 PTA6-PTA0 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 155
... Data direction register B determines whether each port B pin is an input or an output. Writing a logic one to a DDRB bit enables the output buffer for the corresponding port B pin; a logic zero disables the output buffer. Address: Read: Write: Reset: MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor $0001 Bit PTB7 PTB6 PTB5 PTB4 ...
Page 156
... Table 12-2. Port B Pin Functions Accesses to DDRB PTB Bit I/O Pin Mode (1) (2) X Input, Hi-Z DDRB7-DDRB0 X Output DDRB7-DDRB0 I/O Ports Figure 12-8 shows PTBx To Analog-To-Digital Converter 12-2summarizes the operation Accesses to PTB Read/Write Read Write (3) Pin PTB[7:0] Pin PTB[7:0] MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 157
... PTD[7:0] — Port D Data Bits These read/write bits are software programmable. Data direction of each port D pin is under the control of the corresponding bit in data direction register D. Reset has no effect on port D data. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Section $0003 Bit PTD7 PTD6 ...
Page 158
... READ DDRD ($0007) WRITE DDRD ($0007) DDRDx RESET WRITE PTD ($0003) PTDx READ PTD ($0003) Figure 12-11. Port D I/O Circuit I/O Ports Bit 0 DDRD3 DDRD2 DDRD1 DDRD0 Figure 12-11 shows PTDPU[6:7] 5k PTDx PTD[0:3] To Analog-To-Digital Converter PTD[4:5] To Timer MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 159
... DDRx bit is not affected by SLOWDx. PTDPUx — Pull-up Enable The PTDPU6 and PTDPU7 bits enable the 5k pull-up on PTD6 and PTD7 respectively, regardless the status of DDRDx bit. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Table 12-3. Port D Pin Functions I/O Pin PTD Bit Bit Mode (1) ...
Page 160
... I/O Ports Technical Data 158 MC68H(R)C908JL3 I/O Ports Freescale Semiconductor Rev. 1.1 — ...
Page 161
... MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Section 13. External Interrupt (IRQ) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 IRQ1 Pin 161 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . 163 IRQ Status and Control Register (ISCR 163 A dedicated external interrupt pin, IRQ1 ...
Page 162
... When set, the IMASK1 bit in the ISCR mask all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK1 bit is clear. Technical Data 160 Figure 13-1 shows the structure of the IRQ module. External Interrupt (IRQ) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 163
... A logic zero on the IRQ1 pin can latch an interrupt request into the IRQ1 latch. A vector fetch, software clear, or reset clears the IRQ1 latch. If the MODE1 bit is set, the IRQ1 pin is both falling-edge-sensitive and low-level-sensitive. With MODE1 set, both of the following actions must occur to clear IRQ1: MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Control CLR ...
Page 164
... When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. NOTE: An internal pull-up resistor disabled by setting the IRQPUD bit in the CONFIG2 register ($001E). Technical Data 162 is connected to the IRQ1 pin; this can DD External Interrupt (IRQ) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 165
... Address: Read: Write: Reset: MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor (See Section 7. System Integration Module Shows the state of the IRQ1 flag Clears the IRQ1 latch Masks IRQ1 and interrupt request Controls triggering sensitivity of the IRQ1 interrupt pin $001D Bit 7 6 ...
Page 166
... IRQPUD — IRQ1 Pin Pull-up control bit 1 = Internal pull-up is disconnected 0 = Internal pull-up is connected between IRQ1 pin and V Technical Data 164 $001E Bit IRQPUD R R LVIT1 Not affected Not affected Reserved Figure 13-4. Configuration Register 2 (CONFIG2) External Interrupt (IRQ Bit 0 LVIT0 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 167
... Features of the keyboard interrupt module include the following: • • • • MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Keyboard Status and Control Register 169 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 170 Wait Mode 171 Stop Mode ...
Page 168
... KBIE6 KBIE5 KBIE4 Unimplemented ACKK V DD RESET CLR KEYBOARD INTERRUPT FF MODEK Keyboard Interrupt Module (KBI Bit 0 KEYF 0 IMASKK MODEK ACKK KBIE3 KBIE2 KBIE1 KBIE0 INTERNAL BUS VECTOR FETCH DECODER KEYF SYNCHRONIZER Keyboard Interrupt Request IMASKK MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 169
... MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low ...
Page 170
... Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and Technical Data 168 Keyboard Interrupt Module (KBI) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 171
... This read-only bit is set when a keyboard interrupt is pending on port- A. Reset clears the KEYF bit. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor DDRA bits in the data direction register A. keyboard interrupt enable register. Flags keyboard interrupt requests. Acknowledges keyboard interrupt requests. Masks keyboard interrupt requests. ...
Page 172
... Reset clears the keyboard interrupt enable register KBIx pin enabled as keyboard interrupt pin 0 = KBIx pin not enabled as keyboard interrupt pin Technical Data 170 $001B Bit KBIE6 KBIE5 KBIE4 Keyboard Interrupt Module (KBI Bit 0 KBIE3 KBIE2 KBIE1 KBIE0 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 173
... With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Keyboard Interrupt Module (KBI) Keyboard Interrupt Module (KBI) Technical Data 171 ...
Page 174
... Keyboard Interrupt Module (KBI) Technical Data 172 Keyboard Interrupt Module (KBI) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 175
... Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG1 register. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 2OSCOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 Power-On Reset ...
Page 176
... COP module. SIM 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER – 2 2OSCOUT cycles; depending on the state of the Computer Operating Properly (COP) SIM RESET CIRCUIT RESET STATUS REGISTER 18 4 – 2 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 177
... Internal Reset An internal reset clears the SIM counter and the COP counter. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor (RSR).). Register) clears the COP counter and clears bits 12 through 5 Computer Operating Properly (COP) Computer Operating Properly (COP) 7.8.2 Reset Status Figure 15-1 ...
Page 178
... COP module enabled Technical Data 176 (CONFIG).) $001F Bit LVID Reserved Figure 15-2. Configuration Register 1 (CONFIG1) 13 – – 2 Computer Operating Properly (COP) Section 5. Configuration Bit 0 R SSREC STOP COPD × 2OSCOUT cycles 4 ) × 2OSCOUT cycles MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 179
... Wait Mode The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor $FFFF Bit Low byte of reset vector Clear COP counter Unaffected by reset Figure 15-3 ...
Page 180
... COP timeout period after entering or exiting stop mode. 15.9 COP Module During Break Mode The COP is disabled during a break interrupt when V on the RST pin. Technical Data 178 Computer Operating Properly (COP present DD HI MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 181
... LVI trip (LVI 16.3 Features Features of the LVI module include the following: • • MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Section 16. Low Voltage Inhibit (LVI) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 LVI Control Register (CONFIG2/CONFIG1 180 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 Stop Mode ...
Page 182
... LVI = 1 TRIP DD DD LVT0 Figure 16-1. LVI Module Block Diagram $001E Bit IRQPUD R R LVIT1 Not affected Not affected Reserved Figure 16-2. Configuration Register 2 (CONFIG2) Low Voltage Inhibit (LVI) LVID LVI RESET Bit 0 LVIT0 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 183
... The STOP and WAIT instructions put the MCU in low-power- consumption standby modes. 16.6.1 Wait Mode The LVI module, when enabled, will continue to operate in WAIT Mode. 16.6.2 Stop Mode The LVI module, when enabled, will continue to operate in STOP Mode. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor $001F Bit COPRS ...
Page 184
... Low Voltage Inhibit (LVI) Technical Data 182 Low Voltage Inhibit (LVI) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 185
... This section describes the break module. The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Section 17. Break Module (BREAK) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . 186 CPU During Break Interrupts ...
Page 186
... CPU completes its current instruction. A return from interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation. Technical Data 184 Figure 17-1 shows the structure of the break module. Break Module (BREAK) MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 187
... Write: (BRKSCR) Reset: Note: Writing a logic 0 clears SBSW. Figure 17-2. Break I/O Register Summary MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor IAB[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB[15:0] 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB[7:0] Figure 17-1. Break Module Block Diagram ...
Page 188
... Break address register high (BRKH) • Break address register low (BRKL) • Break status register (BSR) • Break flag control register (BFCR) Technical Data 186 7.8.3 Break Flag Control Register (BFCR) Break Module (BREAK present DD HI MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 189
... This read/write status and control bit is set when a break address match occurs. Writing a logic one to BRKA generates a break interrupt. Clear BRKA by writing a logic zero to it before exiting the break routine. Reset clears the BRKA bit. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor $FE0E Bit BRKE ...
Page 190
... Bit Bit Figure 17-5. Break Address Register Low (BRKL) $FE00 Bit Reserved Figure 17-6. Break Status Register (BSR) Break Module (BREAK Bit Bit Bit Bit Bit 0 SBSW (1) Note 0 1. Writing a logic zero clears SBSW. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
Page 191
... DEC LOBYTE,SP RETURN PULH RTI MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor 1 = Stop mode or wait mode was exited by break interrupt 0 = Stop mode or wait mode was not exited by break interrupt ; See if wait mode or stop mode was exited ; by break RETURNLO is not zero, ; then just decrement low byte. ...
Page 192
... A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. See Technical Data 190 $FE03 Reserved Figure 17-7. Break Flag Control Register (BFCR) 7.7 Low-Power Modes). Clear the SBSW bit by writing logic 7.8 SIM Break Module (BREAK Bit Registers. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 18.14 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 18.2 Introduction This section contains electrical and timing specifications. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Section 18. Electrical Specifications Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Functional Operating Range 193 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 5V DC Electrical Characteristics 194 5V Control Timing ...
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... STG I SS MVSS I DD MVDD . SS and V IN ≤ ≤ Reliability of operation is enhanced OUT Electrical Specifications for guaranteed operating (1) Value Unit –0 –0 +0 –0 ±25 mA °C –55 to +150 100 mA 100 mA be constrained to the OUT MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... Constant Average junction temperature Maximum junction temperature NOTES: 1. Power dissipation is a function of temperature constant unique to the device. K can be determined for a known T MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor Table 18-2. Operating Range Characteristic Symbol T V Table 18-3. Thermal Characteristics Characteristic 20-Pin PDIP ...
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... Max Unit Typ — — V — 0.4 V — 0 — 0.3 × V — 1 5.5 mA µ ± 10 µA — ± 1 µA — — — 8 — 100 mV — — V/ms 8.5 — V 3.3 4.8 kΩ kΩ 4.0 4.4 V MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this infor- mation. 3. Minimum pulse width reset is guaranteed to be recognized possible for a smaller pulse width to cause a reset. MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor (1) Symbol = unless otherwise noted. ...
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... MΩ — — See Figure 18-1 EXT C — 10 EXT EXT 5V @ 25° Resistor, R (kΩ) EXT Electrical Specifications Max Unit 32 MHz 12 MHz 32 MHz — — L — L — — — pF MCU OSC1 EXT EXT 50 MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...
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... Digital I/O ports Hi-Z leakage current Input current Capacitance Ports (as input or output) (6) POR rearm voltage (7) POR rise time ramp rate Monitor mode entry voltage (8) Pullup resistors PTD6, PTD7 RST, IRQ1, PTA0–PTA6 LVI reset voltage MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor (1) Symbol ...
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... Table 18-8. Control Timing (3V) (1) Symbol IRL = timing shown with respect to 20 Electrical Specifications (2) Max Unit Typ RST must be driven low externally until Min Max Unit — 4 MHz µs 1.5 — and 70 unless otherwise DD DD MC68H(R)C908JL3 Rev. 1.1 — Freescale Semiconductor ...