MC68HC908AB32CFU Freescale Semiconductor, MC68HC908AB32CFU Datasheet
MC68HC908AB32CFU
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MC68HC908AB32CFU Summary of contents
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MC68HC908AB32 Technical Data M68HC08 Microcontrollers Rev. 1.1 MC68HC908AB32/D August 2, 2005 freescale.com ...
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... Section 15. Serial Communications Interface Section 16. Serial Peripheral Interface Module (SPI 279 Section 17. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 311 Section 18. External Interrupt (IRQ 339 Section 19. Keyboard Interrupt Module (KBI 345 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Module (SCI 239 List of Sections List of Sections Technical Data 3 ...
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... List of Sections Section 20. Computer Operating Properly (COP 353 Section 21. Low-Voltage Inhibit (LVI 359 Section 22. Break Module (BRK 365 Section 23. Electrical Specifications 373 Section 24. Mechanical Specifications . . . . . . . . . . . . . 387 Section 25. Ordering Information . . . . . . . . . . . . . . . . . 389 Technical Data 4 MC68HC908AB32 List of Sections Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Power Supply Pins (V DD Oscillator Pins (OSC1 and OSC2 External Reset Pin (RST External Interrupt Pin (IRQ) ...
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... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 61 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 62 FLASH Program/Read Operation . . . . . . . . . . . . . . . . . . . . . . . 63 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . 66 Wait Mode Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Section 5. EEPROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table of Contents MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 EEPROM Timebase Requirements . . . . . . . . . . . . . . . . . . . . . 72 EEPROM Security Options .72 EEPROM Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 EEPROM Programming and Erasing . . . . . . . . . . . . . . . . . . . . 73 EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 EEPROM Erasing Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Stop Mode ...
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... Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . 117 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SIM Counter during Power-On Reset 118 SIM Counter during Stop Mode Recovery . . . . . . . . . . . . . 118 SIM Counter and Reset States 118 Table of Contents MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 SWI Instruction 121 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . 123 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Stop Mode ...
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... Section 10. Monitor ROM (MON) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 Security 167 Extended Security .168 Table of Contents MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
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... TIMA Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . 187 11.10.4 TIMA Channel Status and Control Registers . . . . . . . . . . . 188 11.10.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 192 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Section 11. Timer Interface Module A (TIMA) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 TIMA Counter Prescaler ...
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... Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 205 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Interrupts .207 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 TIMB During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 208 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 TIMB Clock Pin .209 TIMB Channel I/O Pins 209 Table of Contents MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Section 13. Programmable Interrupt Timer (PIT) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 PIT Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 PIT During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 224 I/O Registers ...
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... Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .254 Receiver Wakeup 257 Receiver Interrupts 258 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 Table of Contents / 234 REFL ). . . . . . . . . . . . . 234 REFH MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 SCI During Break Module Interrupts .260 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 PTE0/TxD (Transmit Data 260 PTE1/RxD (Receive Data 260 I/O Registers 261 SCI Control Register 261 SCI Control Register 264 SCI Control Register 3 ...
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... Data Direction Register B (DDRB 319 Port 320 Port C Data Register (PTC 320 Data Direction Register C (DDRC 321 Port 323 Port D Data Register (PTD 323 Data Direction Register D (DDRD 324 Port D Input Pullup Enable Register (PTDPUE 325 Table of Contents MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Port 326 Port E Data Register (PTE 326 Data Direction Register E (DDRE 328 Port 329 Port F Data Register (PTF 329 Data Direction Register F (DDRF 330 Port F Input Pullup Enable Register (PTFPUE 332 Port G ...
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... COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Interrupts .357 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . 358 Section 21. Low-Voltage Inhibit (LVI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 Table of Contents MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .361 False Reset Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 LVI Status Register (LVISR 362 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363 Stop Mode ...
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... Control Timing 378 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . 378 Section 24. Mechanical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 64-Pin Plastic Quad Flat Pack (QFP 388 Section 25. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Table of Contents MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Title MC68HC908AB32 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 32 64-Pin QFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Memory Map Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .45 FLASH Control Register (FLCR FLASH Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . 65 FLASH Block Protect Start Address . . . . . . . . . . . . . . . . . . . . .66 FLASH Block Protect Register (FLBPR) ...
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... CGM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 CGM I/O Register Summary 134 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . 141 CGM I/O Register Summary 144 PLL Control Register (PCTL 144 PLL Bandwidth Control Register (PBWC 146 PLL Programming Register (PPG 148 List of Figures Page MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
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... TIMB Channel 3 Status and Control Register (TBSC3 215 12-13. CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 12-14 TIMB Channel 0 Register High (TBCH0H 218 12-15 TIMB Channel 0 Register Low (TBCH0L 218 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Title List of Figures List of Figures Page Technical Data 23 ...
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... SCI Status Register 1 (SCS1 269 15-13 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 15-14 SCI Status Register 2 (SCS2 273 15-15 SCI Data Register (SCDR .274 15-16 SCI Baud Rate Register (SCBR 275 Technical Data 24 Title MC68HC908AB32 List of Figures Page Rev. 1.1 — Freescale Semiconductor ...
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... Data Direction Register E (DDRE 328 17-17 Port E I/O Circuit 328 17-18 Port F Data Register (PTF .329 17-19 Data Direction Register F (DDRF 330 17-20 Port F I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Title List of Figures List of Figures Page Technical Data 25 ...
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... SIM Break Status Register (SBSR 371 22-7 SIM Break Flag Control Register (SBFCR 372 23-1 SPI Master Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 23-2 SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 24-1 64-Pin Plastic Quad Flat Pack (QFP 388 Technical Data 26 Title MC68HC908AB32 List of Figures Page Rev. 1.1 — Freescale Semiconductor ...
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... Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . 166 11-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11-2 Prescaler Selection 186 11-3 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . . 191 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Title I/O Pins Summary .38 Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Clock Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 EEPROM Array Address Blocks EEPROM Program/Erase Mode Select ...
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... Port F Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 17-8 Port G Pin Functions 334 17-9 Port H Pin Functions 337 19-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 21-1 LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 25-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Technical Data 28 Title MC68HC908AB32 List of Tables Page Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Power Supply Pins (V DD Oscillator Pins (OSC1 and OSC2 External Reset Pin (RST External Interrupt Pin (IRQ ...
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... Low-power design (fully static with STOP and WAIT modes) • Master reset pin and power-on reset 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 30 General Description 1 feature MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
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... MCU Block Diagram Figure 1-1 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor 51 general-purpose input/output (I/O) pins: – 30 shared-function I/O pins – 5-bit keyboard wakeup port – Selectable pullups on inputs on port D and port F System protection features – Optional computer operating properly (COP) reset – ...
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M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 80 BYTES USER FLASH — 32,256 BYTES USER RAM — 1024 BYTES USER EEPROM — 512 BYTES MONITOR ROM — 307 BYTES USER FLASH VECTORS — 48 BYTES ...
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... NC 9 PTF7 10 PTF5/TBCH1 11 PTF6 12 PTE0/TxD 13 PTE1/RxD 14 PTE2/TACH0 15 PTE3/TACH1 16 Figure 1-2. 64-Pin QFP Pin Assignment MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor shows the pin assignment for the MC68HC908AB32. General Description General Description PTH0/KBD3 48 PTD3 47 PTD2 46 A /VREFL 45 VSS V 44 DDAREF PTD1 43 PTD0 ...
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... MCU operation. SS Technical Data 34 and are the power supply and ground pins. The MCU operates SS MCU 0.1 µ NOTE: Component values shown represent typical applications. Figure 1-3. Power Supply Bypassing General Description Figure 1 (SPI). MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
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... Analog Ground Pin (A The A the analog to digital convertor (ADC) and should be decoupled as per the V SS MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Section 9. Clock Generator Module Section 8. System Integration Module Section 18. External Interrupt ) DDA is the power supply pin for the clock generator module (CGM). ) ...
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... MCLK. See Technical Data 36 ) analog supply pin is used only for the supply connections (CGM). Ports. Section 14. Analog-to-Digital Converter (ADC) Ports. Section 17. Input/Output (I/O) General Description . DDAREF and Ports. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
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... Port H I/O Pins (PTH1/KBD4–PTH0/KBD3) PTH1–PTH0 are general-purpose bidirectional I/O pins with Keyboard wakeup function. See and MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor and Section 12. Timer Interface Module B (SPI), (TIMA), and Section 17. Input/Output (I/O) Section 11. Timer Interface Module A Ports. ...
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... Input (Hi-Z) No Input (Hi-Z) No Input (Hi-Z) Yes Input (Hi-Z) Yes Input (Hi-Z) Yes Input (Hi-Z) Yes Input (Hi-Z) Yes Input (Hi-Z) Yes Input (Hi-Z) Yes Input (Hi-Z) Yes Input (Hi-Z) Yes Input (Hi-Z) Yes Input (Hi-Z) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
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... RST Details of the clock connections to each of the modules on the MC68HC908AB32 are shown in clock source is also given in MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Table 1-1. I/O Pins Summary Function General purpose I/O / Timer B channel 0 General purpose I/O / Timer B channel 3 General purpose I/O ...
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... Bus clock CGMXCLK or bus clock ROM Bus clock RAM Bus clock SPI SPSCK SCI CGMXCLK TIMA Bus clock or PTD6/TACLK TIMB Bus clock or PTD4/TBCLK PIT Bus clock KBI Bus clock General Description Description Clock)) Clock Source MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
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... Accessing an unimplemented location can cause an illegal address reset if illegal address resets are enabled. In the memory map (Figure locations are shaded. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Section 2. Memory Map Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . 41 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Input/Output (I/O) Section Figure 2-1, includes: ...
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... FLASH block protect register, FLBPR • $FFFF; COP control register, COPCTL Data registers are shown in locations. Technical Data 42 Figure 2-1 and in register figures in this document, Figure 2-2, Table 2-1 MC68HC908AB32 Memory Map is a list of vector Rev. 1.1 — Freescale Semiconductor ...
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... MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor $0000 I/O Registers ↓ $004F $0050 ↓ 1,024 Bytes $044F $0450 Unimplemented ↓ 176 Bytes $04FF $0500 ↓ 128 Bytes $057F $0580 Unimplemented ↓ 640 Bytes $07FF $0800 ↓ 512 Bytes $09FF $0A00 Unimplemented ↓ ...
Page 44
... FLASH Block Protect Register (FLBPR) $FF7F Unimplemented ↓ 65 Bytes $FFBF $FFC0 Reserved FLASH Memory ↓ 16 Bytes Reserved for Compatibility with HC08AB16/24/32 $FFCF $FFD0 FLASH Vectors ↓ 48 Bytes $FFFF Figure 2-1. Memory Map (Continued) Memory Map MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 45
... Port E Data Register $0008 Write: (PTE) Reset: Read: Port F Data Register $0009 Write: (PTF) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 11) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Bit PTA7 PTA6 PTA5 PTA4 Unaffected by reset PTB7 PTB6 PTB5 PTB4 Unaffected by reset 0 ...
Page 46
... Bit 0 0 PTG2 PTG1 PTG0 0 0 PTH1 PTH0 DDRE3 DDRE2 DDRE1 DDRE0 DDRF3 DDRF2 DDRF1 DDRF0 DDRG2 DDRG1 DDRG0 DDRH1 DDRH0 CPHA SPWOM SPE SPTIE SPTE MODFEN SPR1 SPR0 WAKE ILTY PEN PTY Reserved MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 47
... Reset: Read: PLL Control Register $001C Write: (PCTL) Reset: Read: PLL Bandwidth Control $001D Register Write: (PBWC) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 11) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Bit SCTIE TCIE SCRIE ILIE Unaffected Unaffected SCTE TC ...
Page 48
... CH0IE MS0B MS0A Bit Indeterminate after reset = Unimplemented Memory Map Bit 0 VRS7 VRS6 VRS5 VRS4 COPRS STOP COPD PS2 PS1 PS0 KBIE3 KBIE2 KBIE1 KBIE0 Bit Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit Reserved MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 49
... Read: Timer A Channel 3 $0030 Register High Write: (TACH3H) Reset: Read: Timer A Channel 3 $0031 Register Low Write: (TACH3L) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 11) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Bit Bit Indeterminate after reset CH1F 0 CH1IE MS1A ...
Page 50
... ADCO ADCH4 AD7 AD6 AD5 AD4 ADIV2 ADIV1 ADIV0 ADICLK Unimplemented Memory Map Bit 0 ELS2B ELS2A TOV2 CH2MAX Bit Bit 0 ELS3B ELS3A TOV3 CH3MAX Bit Bit 0 ADCH3 ADCH2 ADCH1 ADCH0 AD3 AD2 AD1 AD0 Reserved MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 51
... Read: Timer B Channel 0 Status $0045 and Control Register Write: (TBSC0) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 11) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Bit PTDPUE7 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0 PTFPUE7 PTFPUE6 PTFPUE5 PTFPUE4 PTFPUE3 PTFPUE2 PTFPUE1 PTFPUE0 ...
Page 52
... Indeterminate after reset Bit Indeterminate after reset POF 0 POIE PSTOP 0 PRST Bit Bit Bit Bit Unimplemented Memory Map Bit Bit Bit 0 ELS1B ELS1A TOV1 CH1MAX Bit Bit 0 0 PPS2 PPS1 PPS0 Bit Bit Bit Bit Reserved MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 53
... Reserved Write: Reset: Read: $FE07 Reserved Write: Reset: Read: FLASH Control Register $FE08 Write: (FLCR) Reset: Read: $FE09 Reserved Write: Reset: Figure 2-2. Control, Status, and Data Registers (Sheet 9 of 11) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Bit POR PIN COP ILOP ...
Page 54
... Unaffected by reset; $FF when blank EEDIVSECD Contents of EEDIVHNVR ($FE10) EEDIV7 EEDIV6 EEDIV5 EEDIV4 Contents of EEDIVLNVR ($FE11) = Unimplemented Memory Map Bit Bit Bit EEDIV10 EEDIV9 EEDIV8 EEDIV3 EEDIV2 EEDIV1 EEDIV0 R EEDIV10 EEDIV9 EEDIV8 EEDIV3 EEDIV2 EEDIV1 EEDIV0 R = Reserved MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 55
... Reset: * Non-volatile FLASH register; write by programming. Read: COP Control Register $FFFF Write: (COPCTL) Reset: Figure 2-2. Control, Status, and Data Registers (Sheet 11 of 11) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Bit CON3 CON2 CON1 EEPRTCT Unaffected by reset; $FF when blank 0 EEDUM EEOFF EERAS1 ...
Page 56
... PLL Vector (High) $FFF9 PLL Vector (Low) $FFFA IRQ Vector (High) $FFFB IRQ Vector (Low) $FFFC SWI Vector (High) $FFFD SWI Vector (Low) $FFFE Reset Vector (High) Highest $FFFF Reset Vector (Low) Memory Map Vector MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 57
... RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE: For M6805 compatibility, the H register is not stacked. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Random-Access Memory (RAM) Technical Data 57 ...
Page 58
... The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Technical Data 58 Random-Access Memory (RAM) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 59
... FLASH array is organized into two rows per page basis. For the 32K word by 8-Bit Embedded FLASH Memory, the page size is 128 bytes per MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Section 4. FLASH Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . 61 FLASH Mass Erase Operation ...
Page 60
... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 60 ; FLASH control register. $FE08 Bit Figure 4-1. FLASH Control Register (FLCR) FLASH Memory Bit 0 HVEN MASS ERASE PGM MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 61
... Set the HVEN bit. 6. Wait for a time Clear the ERASE bit. 8. Wait for a time, t MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor 1 = MASS erase operation selected 0 = MASS erase operation unselected 1 = Erase operation selected 0 = Erase operation unselected 1 = Program operation selected 0 = Program operation unselected register. ...
Page 62
... Technical Data 62 (typ. 1µs), the memory can be accessed again in rcv (min. 10µs) nvs (min. 4ms) MErase (min. 100µs) nvhl (min. 1µs), the memory can be accessed again in rcv (see 10.5 MC68HC908AB32 FLASH Memory Security), write to the FLASH Rev. 1.1 — Freescale Semiconductor ...
Page 63
... PGM bit, must not exceed the maximum programming time, t This program sequence is repeated throughout the memory until all data is programmed. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor (Figure 4-2 operation and enables the latching of address and data for programming. range desired. (min. 10µs). ...
Page 64
... The FLBPR itself can be erased or programmed only with an external voltage, V also allows entry from reset into the monitor mode. Technical Data 64 PROG Characteristics. 4.8.1 FLASH Block Protect , present on the IRQ pin. This voltage TST MC68HC908AB32 FLASH Memory maximum. See 23.13 Rev. 1.1 — Freescale Semiconductor ...
Page 65
... PROG This row program algorithm assumes the row programmed are initially erased. Figure 4-2. FLASH Programming Flowchart MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor 1 Set PGM bit 2 Read the FLASH block protect register 3 Write any data to any FLASH address within the row address range desired ...
Page 66
... U = Unaffected by reset. Initial value from factory is 1. Write to this register programming sequence to the FLASH memory. Figure 4-3. FLASH Block Protect Register (FLBPR) 1 FLBPR value Figure 4-4. FLASH Block Protect Start Address FLASH Memory Bit 0 BPR3 BPR2 BPR1 BPR0 16-bit memory address MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 67
... Standby Mode is the power saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH minimum. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor BPR[7:0] Start of Address of Protect Range $00 The entire FLASH memory is protected. $01 (0000 0001) $02 (0000 0010) and so on ...
Page 68
... FLASH Memory Technical Data 68 MC68HC908AB32 FLASH Memory Rev. 1.1 — Freescale Semiconductor ...
Page 69
... Introduction This section describes the 512 bytes electrically erasable programmable read-only-memory (EEPROM). MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 EEPROM Timebase Requirements . . . . . . . . . . . . . . . . . . . . . 72 EEPROM Security Options .72 EEPROM Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 EEPROM Programming and Erasing . . . . . . . . . . . . . . . . . . . . 73 EEPROM Programming ...
Page 70
... Unaffected by reset; $FF when blank; factory programmed $10 0 EEDUM EEOFF EERAS1 EEPROM Bit 0 R EEDIV10 EEDIV9 EEDIV8 EEDIV3 EEDIV2 EEDIV1 EEDIV0 R EEDIV10 EEDIV9 EEDIV8 EEDIV3 EEDIV2 EEDIV1 EEDIV0 EEBP3 EEBP2 EEBP1 EEBP0 EERAS0 EELAT AUTO EEPGM MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 71
... MCU reset. The values in these read/write, volatile registers define the EEPROM configurations. For EENVR, the corresponding volatile register is the EEPROM array configuration register (EEACR). MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor CON3 CON2 CON1 EEPRTCT Contents of EENVR ($FE1C) = Unimplemented Security option ...
Page 72
... EEPROM For the EEDIVNVR (two 8-bit registers: EEDIVHNVR and EEDIVLNVR), the corresponding volatile register is the EEPROM timebase divider register (EEDIV: EEDIVH and EEDIVL) Technical Data 72 MC68HC908AB32 EEPROM Freescale Semiconductor Rev. 1.1 — ...
Page 73
... The 512 bytes of EEPROM is divided into four 128-byte blocks. Each of these blocks can be protected from erase/program operations by setting the EEBPx bit in the EENVR. the blocks. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Reference frequency (Hz) × 35 × EEDIV = INT and Register). The 16-byte EEPROM locations from $08F0 to $08FF are protected from erase and program operations ...
Page 74
... Technical Data 74 Table 5-1. EEPROM Array Address Blocks Block Number (EEBPx) EEBP0 EEBP1 EEBP2 EEBP3 EEPROM Address Range $0800–$087F $0880–$08FF $0900–$097F $0980–$09FF MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 75
... Once EEPGM is set, do not read any EEPROM locations, otherwise the current program cycle will be unsuccessful. When EEPGM is set, the on-board programming sequence will be activated. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ( step 7 if AUTO is set program the byte. EEPGM , for the programming voltage to fall. EEFPV Go to step 8 ...
Page 76
... Poll the EEPGM bit until it is cleared by the internal timer. 8. Clear EELAT bits. Technical Data 76 . However, on other MCUs, this delay time may be different. (A) (B) (C) for byte erase; t EBYTE for bulk erase. EBULK , for the erasing voltage to fall. EEFPV (E) EEPROM (B) (B) for block erase; EBLOCK (D) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 77
... Wait Mode The WAIT instruction does not affect the EEPROM possible to start the program or erase sequence on the EEPROM and put the MCU in wait mode. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor / However, on other MCUs, this delay time EBYTE EBLOCK EBULK EEPROM ...
Page 78
... This read/write register controls programming/erasing of the EEPROM array. Address: Read: Write: Reset: EEDUM — Dummy Bit This read/write bit has no function. Technical Data 78 $FE1D Bit EEDUM EEOFF EERAS1 Figure 5-2. EEPROM Control Register (EECR) EEPROM Bit 0 EERAS0 EELAT AUTO EEPGM MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 79
... AUTO — Automatic termination of program/erase cycle When AUTO is set, EEPGM is cleared automatically after the program/erase cycle is terminated by the internal timer. (See note D for Erasing.) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor 1 = Disable EEPROM array 0 = Enable EEPROM array Table 5-2. EEPROM Program/Erase Mode Select EEBPx EERAS1 0 0 ...
Page 80
... The EEPRTCT bit is used to enable the security feature in the EEPROM (see 1 = EEPROM security disabled 0 = EEPROM security enabled Technical Data 80 $FE1F Bit CON3 CON2 CON1 EEPRTCT Contents of EENVR ($FE1C) 5.7 EEPROM Security EEPROM Bit 0 EEBP3 EEBP2 EEBP1 EEBP0 Options). MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 81
... EEDIVH and EEDIVL. The 11-bit value in this register is used to configure the timebase divider circuit to obtain the 35µs timebase for EEPROM control. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor 1 = EEPROM array block is protected 0 = EEPROM array block is unprotected Block Number (EEBPx) EEBP0 EEBP1 ...
Page 82
... Figure 5-5. EEPROM Divider Register High (EEDIVH) $FE1B Bit EEDIV7 EEDIV6 EEDIV5 EEDIV4 Contents of EEDIVLNVR ($FE11) Figure 5-6. EEPROM Divider Register Low (EEDIVL) EEPROM Bit 0 R EEDIV10 EEDIV9 EEDIV8 Bit 0 EEDIV3 EEDIV2 EEDIV1 EEDIV0 6.5 Configuration Register 2) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 83
... Read: Write: Reset: Figure 5-7. EEPROM Divider Non-volatile Register High(EEDIVHNVR) Address: Read: Write: Reset: Figure 5-8. EEPROM Divider Non-volatile Register Low (EEDIVLNVR) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Reference frequency (Hz) × 35 × EEDIV = INT $FE10 Bit EEDIVSECD Unaffected by reset; $FF when blank ...
Page 84
... EEDIVHNVR and EEDIVLNVR. Modifications to the EEDIVH and EEDIVL registers are also disabled. Therefore, care should be taken before programming a value into the EEDIVHNVR. Technical Data 84 Register), or programmed to a logic 1 in the MC68HC908AB32 EEPROM 5.11.3 EEPROM Rev. 1.1 — Freescale Semiconductor ...
Page 85
... MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Functional description Configuration Register Configuration Register Low-voltage inhibit (LVI) in stop mode LVI reset LVI module power Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles) 18 COP timeout period (2 – ...
Page 86
... LVIRSTD disables the reset signal from the LVI module. (See Section 21. Low-Voltage Inhibit 1 = LVI module resets disabled 0 = LVI module resets enabled Technical Data 86 $001F Bit LVIRSTD LVIPWRD Reserved Figure 6-1. Configuration Register 1 (CONFIG1) (LVI).) (LVI).) Configuration Register (CONFIG Bit 0 SSREC COPRS STOP COPD Section MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 87
... AB, AS, and AZ families doubt, check with your local field applications representative. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor (LVI).) 1 = LVI module power disabled 0 = LVI module power enabled 1 = STOP mode recovery after 32 CGMXCLK cycles 0 = STOP mode recovery after 4096 CGMXCLK cycles ...
Page 88
... AB, AS, and AZ families doubt, check with your local field applications representative. Technical Data 88 $003F Bit EEDIVCLK Reserved Figure 6-2. Configuration Register 2 (CONFIG2) Section 5. Configuration Register (CONFIG Bit EEPROM.) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 89
... M68HC05 CPU. The CPU08 Reference Manual (Freescale document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Section 7. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Stack Pointer ...
Page 90
... Low-power stop and wait modes 7.4 CPU Registers Figure 7-1 the memory map. Technical Data 90 shows the five CPU registers. CPU registers are not part of Central Processor Unit (CPU) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 91
... Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: Write: Reset: MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Figure 7-1. CPU Registers Bit Unaffected by reset Figure 7-2. Accumulator (A) Central Processor Unit (CPU) ...
Page 92
... The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Technical Data 92 Bit Indeterminate Figure 7-3. Index Register (H:X) Central Processor Unit (CPU) Bit MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 93
... Read: Write: Reset: 7.4.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Bit ...
Page 94
... The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor Carry between bits 3 and carry between bits 3 and 4 Technical Data 94 Bit Indeterminate Figure 7-6. Condition Code Register (CCR) Central Processor Unit (CPU Bit MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 95
... Z — Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor 1 = Interrupts disabled 0 = Interrupts enabled 1 = Negative result 0 = Non-negative result 1 = Zero result 0 = Non-zero result Central Processor Unit (CPU) ...
Page 96
... Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock Technical Data 96 Central Processor Unit (CPU) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 97
... Opcode Map See MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock ...
Page 98
... EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 99
... Branch if Interrupt Mask Set BNE rel Branch if Not Equal BPL rel Branch if Plus BRA rel Branch Always MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Description PC ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? (N ⊕ ← (PC rel ? ( ⊕ ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( ← ...
Page 100
... DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR IMM IMM IX1 IX SP1 9E61 DIR INH 4F 1 INH 5F 1 INH 8C 1 IX1 SP1 9E6F ff 4 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 101
... Decrement DEC opr,X DEC ,X DEC opr,SP DIV Divide MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Description (A) – (M) M ← (M) = $FF – (M) A ← (A) = $FF – (M) X ← (X) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) (H:X) – (M (X) – ...
Page 102
... FD 4 IMM DIR EXT IX2 – IX1 SP1 9EE6 ff 4 SP2 9ED6 IMM – DIR IMM DIR EXT IX2 – IX1 SP1 9EEE ff 4 SP2 9EDE DIR INH 48 1 INH 58 1 IX1 SP1 9E68 ff 5 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 103
... Pull H from Stack PULX Pull X from Stack ROL opr ROLA ROLX Rotate Left through Carry ROL opr,X ROL ,X ROL opr,SP MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Description ← (M) (M) Destination Source H:X ← (H: (IX+D, DIX+) X:A ← (X) × (A) M ← –(M) = $00 – (M) A ← ...
Page 104
... SP1 9E66 INH IMM DIR EXT IX2 IX1 SP1 9EE2 ff 4 SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 105
... TSX Transfer SP to H:X TXA Transfer TXS Transfer H MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Description A ← (A) – (M) PC ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← ...
Page 106
... Zero bit & Logical AND | Logical OR ⊕ Logical EXCLUSIVE Contents of –( ) Negation (two’s complement) # Immediate value « Sign extend ← Loaded with ? If : Concatenated with Set or cleared — Not affected Central Processor Unit (CPU) CCR MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 107
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR 1 INH ...
Page 108
... Central Processor Unit (CPU) Technical Data 108 Central Processor Unit (CPU) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 109
... MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 112 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Clock Start-Up from POR or LVI Reset . . . . . . . . . . . . . . . 113 Clocks in Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . 113 Reset and System Initialization 113 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Active Resets from Internal Sources ...
Page 110
... SIM Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 127 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . 128 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . 129 Figure 8-1. Figure 8 summary of the SIM I/O registers. shows the internal signal names used in this section. System Integration Module (SIM) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 111
... Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor STOP/WAIT CONTROL SIM COUNTER ÷ 2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL MASTER ...
Page 112
... CGMOUT ÷ When CGMOUT = B PTC3 CGM Figure 8-3. CGM Clock Signals System Integration Module (SIM Bit 0 SBSW Note ILAD 0 LVI Reserved R Figure 8-3. This clock can come (CGM). SIM COUNTER ÷ BUS CLOCK 2 GENERATORS SIM MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 113
... MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Section 9. Clock Generator Module Power-on reset module (POR) External reset pin (RST) Computer operating properly module (COP) Low-voltage inhibit module (LVI) Illegal opcode Illegal address System Integration Module (SIM) System Integration Module (SIM) (CGM) ...
Page 114
... An internal reset can be caused by an illegal address, illegal 8-5. System Integration Module (SIM) 8.5 SIM Counter), but an 8.8 SIM Registers.) Table 8-2 for details. 4163 (4096 + ( VECT H VECT L Figure 8-6. Note that for LVI or MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 115
... At power-on, the following events occur: • • • • MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor IRST RST PULLED LOW BY MCU RST 32 CYCLES IAB Figure 8-5. Internal reset timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST ...
Page 116
... During a break state, V RST pin disables the COP module. Technical Data 116 32 32 CYCLES CYCLES Figure 8-7. POR Recovery 13 4 – 2 CGMXCLK cycles, drives the COP System Integration Module (SIM) $FFFE $FFFF TST on the TST MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 117
... COP module. The SIM counter is 13 bits long and is clocked by the falling edge of CGMXCLK. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor voltage falls to the trip voltage System Integration Module (SIM) System Integration Module (SIM) . The LVI bit in the SIM reset ...
Page 118
... Normal, sequential program execution can be changed in three different ways: • Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) • Reset • Break interrupts Technical Data 118 System Integration Module (SIM) 8.7.2 Stop Mode for counter control and MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 119
... Once an interrupt is latched by the SIM, no other interrupt may take precedence, regardless of priority, until the latched interrupt is serviced (or the I-bit is cleared). (See MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Figure 8-8 shows interrupt recovery timing – – – – ...
Page 120
... AS MANY INTERRUPTS LOAD PC WITH INTERRUPT VECTOR AS EXIST ON CHIP FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES INSTRUCTION? NO Figure 8-10. Interrupt Processing System Integration Module (SIM) STACK CPU REGISTERS SET I-BIT UNSTACK CPU REGISTERS EXECUTE INSTRUCTION MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 121
... NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC – hardware interrupt does. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor CLI LDA #$FF INT1 PSHH PULH RTI INT2 ...
Page 122
... PLL Vector (High) $FFF9 PLL Vector (Low) $FFFA IRQ Vector (High) $FFFB IRQ Vector (Low) $FFFC SWI Vector (High) $FFFD SWI Vector (Low) $FFFE Reset Vector (High) Highest $FFFF Reset Vector (Low) System Integration Module (SIM) Vector MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 123
... Upon leaving break mode, execution of the second step will clear the flag as normal. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor (BRK). The SIM puts the CPU into the break System Integration Module (SIM) System Integration Module (SIM) Technical Data 123 ...
Page 124
... WAIT ADDR WAIT ADDR + 1 PREVIOUS DATA NEXT OPCODE last instruction. Figure 8-12. Wait Mode Entry Timing and Figure 8-14 show the timing for wait recovery. System Integration Module (SIM) SAME SAME SAME SAME MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 125
... CGMXCLK cycles down to 32. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. NOTE: External crystal applications should use the full stop recovery time by clearing the SSREC bit. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor IAB $6E0B $6E0C IDB $A6 $A6 $A6 $01 Figure 8-13 ...
Page 126
... IAB STOP ADDR STOP ADDR + 1 IDB PREVIOUS DATA NEXT OPCODE R/W instruction. Figure 8-15. Stop Mode Entry Timing STOP RECOVERY PERIOD STOP + 2 STOP + 2 SP System Integration Module (SIM) SAME SAME SAME SAME SP – – – 3 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 127
... SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. The following code is an example of this. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Table 8-4. SIM Registers Address Register $FE00 SBSR ...
Page 128
... Else deal with high byte, too. ; Point to STOP/WAIT opcode. ; Restore H register. $FE01 Bit POR PIN COP ILOP Unimplemented Figure 8-18. SIM Reset Status Register (SRSR) System Integration Module (SIM Bit 0 ILAD 0 LVI MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 129
... MCU break state. To clear status bits during the break state, the BCFE bit must be set. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor 1 = Last reset caused by external reset pin (RST POR or read of SRSR 1 = Last reset caused by COP counter 0 = POR or read of SRSR ...
Page 130
... System Integration Module (SIM) Technical Data 130 System Integration Module (SIM) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 131
... MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Phase-Locked Loop (PLL) Circuit . . . . . . . . . . . . . . . . . . . 135 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . 136 Manual and Automatic PLL Bandwidth Modes . . . . . . . 136 Programming the PLL ...
Page 132
... Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 151 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . 151 Acquisition/Lock Time Definitions .152 Parametric Influences On Reaction Time 153 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . . 154 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . . 155 Clock Generator Module (CGM) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 133
... DETECTOR LOCK CGMVDV MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Crystal oscillator circuit which generates the constant crystal frequency clock, CGMXCLK. Phase-locked loop (PLL) which generates the programmable VCO frequency clock CGMVCLK. Base clock selector circuit; this software-controlled circuit selects either CGMXCLK divided by two or the VCO clock CGMVCLK divided by two, as the base clock CGMOUT ...
Page 134
... OSC1 pin and the OSC2 pin allowed to float. Technical Data 134 Bit PLLF PLLIE PLLON BCS LOCK AUTO ACQ XLD MUL7 MUL6 MUL5 MUL4 Unimplemented Clock Generator Module (CGM Bit VRS7 VRS6 VRS5 VRS4 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 135
... The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock, CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The loop filter MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Voltage-controlled oscillator (VCO) Modulo VCO frequency divider Phase detector Loop filter Lock detector VRS , (4 ...
Page 136
... Acquisition and Tracking . The circuit determines the mode of the PLL and the lock RDV (PBWC). 9.4.3 Base Clock Selector Clock Generator Module (CGM) Modes. The value of the 9.6.2 PLL Bandwidth Circuit. The PLL is MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 137
... Such systems typically operate well below f MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor 9.6.2 PLL Bandwidth Control Register 9.7 Interrupts for information and precautions on using interrupts). The ACQ bit (see 9 ...
Page 138
... Choose a practical PLL reference frequency Select a VCO frequency multiplier, N. Technical Data 138 (see 9.10 Acquisition/Lock Time ACQ AL × VCLKDES BUSDES f VCLKDES --------------------- - N = round f RCLK Clock Generator Module (CGM) , after entering tracking mode . BUSDES . RCLK MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 139
... meaningless when used in the equations given. To account for these exceptions: MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor 5. Calculate and verify the adequacy of the VCO and bus frequencies f and f VCLK 6. Select a VCO linear range multiplier, L. ...
Page 140
... The oscillator configuration uses five components: Technical Data 140 Figure 9-3. This figure shows only the logical Clock Generator Module (CGM) 9.4.3 Base Clock Selector MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 141
... SIMOSCEN OSC1 can be zero (shorted) when used with higher-frequency crystals. Refer to manufacturer’s data. S MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Crystal Fixed capacitor Tuning capacitor, C (can also be a fixed capacitor) 2 Feedback resistor Series resistor, R (optional included in the diagram to follow strict Pierce ...
Page 142
... The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and PLL. Technical Data 142 should be placed as close to the F connection DDA carefully for maximum noise immunity and place bypass DDA Clock Generator Module (CGM) pin. DD MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 143
... The following registers control and monitor operation of the CGM: • • • Figure 9-4 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ) and is generated directly from the crystal oscillator XCLK Figure 9-3 shows only the logical relation of CGMXCLK to OSC1 PLL control register (PCTL). (See (PCTL)) PLL bandwidth control register (PBWC). (See Bandwidth Control Register PLL programming register (PPG) ...
Page 144
... PLLIE PLLON BCS LOCK AUTO ACQ XLD MUL7 MUL6 MUL5 MUL4 Unimplemented $001C Bit PLLF PLLIE PLLON BCS Unimplemented Figure 9-5. PLL Control Register (PCTL) Clock Generator Module (CGM Bit VRS7 VRS6 VRS5 VRS4 Bit MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 145
... BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one source clock to MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor 1 = PLL interrupts enabled 0 = PLL interrupts disabled 1 = Change in lock condition change in lock condition 1 = PLL on ...
Page 146
... Technical Data 146 Circuit. Reset and the STOP instruction clear 9.4.3 Base Clock Selector $001D Bit LOCK AUTO ACQ XLD Unimplemented Figure 9-7. PLL Bandwidth Control Register (PBWC) Clock Generator Module (CGM) 9.4.3 Circuit Bit MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 147
... Write XLD. 2. Wait 4 × N cycles the VCO frequency multiplier.) 3. Read XLD. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor 1 = Automatic bandwidth control 0 = Manual bandwidth control 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked 1 = Tracking mode 0 = Acquisition mode 1 = Crystal reference is not active ...
Page 148
... Reset initializes these bits give a default multiply value of 6. Technical Data 148 $001E Bit MUL7 MUL6 MUL5 MUL4 Figure 9-8. PLL Programming Register (PPG) PLL). A value the multiplier select Clock Generator Module (CGM Bit 0 VRS7 VRS6 VRS5 VRS4 9.4.2.1 PLL Circuits and MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 149
... VCO range select bits are all clear. The VCO range select bits must be programmed correctly. Incorrect programming may result in failure of the PLL to achieve lock. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Table 9-1. VCO Frequency Multiplier (N) Selection MUL7:MUL6:MUL5:MUL4 0000 0001 0010 ...
Page 150
... PLL without turning it off. Applications that require the PLL to wake the MCU from WAIT mode also can deselect the PLL output without turning off the PLL. Technical Data 150 Clock Generator Module (CGM) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 151
... The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor (SIM). Clock Generator Module (CGM) Clock Generator Module (CGM) Section 8. System Integration Technical Data ...
Page 152
... PLL takes to reduce the error ACQ , of not more than ±100%. In automatic – f )/f DES ORIG DES 9.4.2.3 Manual and Automatic PLL Modes), acquisition time expires when the ACQ bit Clock Generator Module (CGM) . TRK MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 153
... PLL may not be able to adjust the voltage in a reasonable time. See MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Lock time the time the PLL takes to reduce the error LOCK between the actual output frequency and the desired output frequency to less than the lock mode entry tolerance ∆ ...
Page 154
... Technical Data 154 9.10.2 Parametric Influences On Reaction is critical to the stability and reaction time ------------ - F FACT f RDV , the voltage potential at which the MCU is DDA Clock Generator Module (CGM) . The DDA Time, the DDA MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 155
... Manual and Automatic PLL Bandwidth clock cycles, n tracking mode entry tolerance ∆ Also, a certain number of clock cycles, n MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Correct selection of filter capacitor, C (see 9.10.3 Choosing a Filter Room temperature operation Negligible external leakage on CGMXFC Negligible noise is the K factor when the PLL is configured in acquisition mode, and is the K factor when the PLL is configured in tracking mode. See ...
Page 156
... Influences On Reaction Time Technical Data 156 , is an integer multiple of n ACQ , is an integer multiple calculated above. may slow the lock time considerably. Clock Generator Module (CGM) . LOCK /f , ACQ RDV /f . TRK RDV 9.4.3 Base Clock Selector 9.10.2 Parametric MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 157
... This section describes the monitor ROM (MON). The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Section 10. Monitor ROM (MON) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Data Format ...
Page 158
... No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Technical Data 158 1 Figure 10-1 shows a example circuit used to enter monitor Monitor ROM (MON) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 159
... MC145407 + 10 µ µ DB- NOTES: Position A — Bus clock = CGMXCLK ÷ CGMVCLK ÷ 4 Position B — Bus clock = CGMXCLK ÷ 2 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor µ µ MC74HC125 Figure 10-1. Monitor Mode Circuit Monitor ROM (MON) Monitor ROM (MON MC68HC908AB32 10 kΩ ...
Page 160
... Specifications. TST Specifications) is applied to either the IRQ pin Section 8. System Integration Module (SIM) Monitor ROM (MON) Bus Frequency CGMOUT (CGMOUT ÷ 2) CGMXCLK ÷ 2 CGMXCLK ÷ CGMVCLK ÷ 2 CGMVCLK ÷ 4 CGMXCLK CGMXCLK ÷ 2 (see TST for MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 161
... The data transmit and receive rate can be anywhere from 4800 baud to 28.8 k-baud. Transmit and receive baud rates must be identical. START BREAK MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor is a summary of the differences between user mode and Table 10-2. Mode Differences Reset COP Vector High ...
Page 162
... ROM immediately echoes each READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW Figure 10-4. Read Transaction MISSING STOP BIT Figure 10-5. Break Transaction Monitor ROM (MON) DATA RESULT Figure 10-5.) TWO-STOP-BIT DELAY BEFORE ZERO ECHO MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 163
... A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64k-byte memory map. Description MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor READ, read memory WRITE, write memory IREAD, indexed read IWRITE, indexed write READSP, read stack pointer RUN, run user program Table 10-3 ...
Page 164
... Read next 2 bytes in memory from last address accessed Specifies 2-byte address in high byte:low byte order Returns contents of next two addresses $1A Command Sequence SENT TO MONITOR IREAD IREAD ECHO Monitor ROM (MON) DATA DATA LOW DATA DATA RETURN MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 165
... Description Operand Returned Description Operand Returned MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Table 10-6. IWRITE (Indexed Write) Command Write to last address accessed + 1 Specifies single data byte Data None Opcode $19 Command Sequence SENT TO MONITOR IWRITE IWRITE ECHO Table 10-7. READSP (Read Stack Pointer) Command ...
Page 166
... Executes RTI instruction None None $28 Command Sequence SENT TO MONITOR RUN RUN ECHO Table 10-9. Monitor Baud Rate Selection VCO Frequency Multiplier ( 4800 9600 14,400 4096 8192 12,288 Monitor ROM (MON) (CGM).) 19,200 24,000 28,800 16,384 20,480 24,576 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 167
... RST PTA0 NOTES Echo delay, 2 bit times 2 = Data return delay, 2 bit times 4 = Wait 1 bit time before sending next byte. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Figure 4096 + 32 CGMXCLK CYCLES 256 BUS CYCLES (MINIMUM) FROM HOST FROM MCU Figure 10-6. Monitor Mode Entry Timing ...
Page 168
... FLASH memory cannot be erased without a valid security code (matching $FFF6–$FFFD). Therefore, the extended security command keyword should not be programmed during software development. Technical Data 168 10.5 Security. Monitor ROM (MON) 10.5 Security, the MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 169
... TIMA Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . 187 11.10.4 TIMA Channel Status and Control Registers . . . . . . . . . . . 188 11.10.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 192 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 TIMA Counter Prescaler .171 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Output Compare ...
Page 170
... External TIMA clock input (4MHz maximum frequency) • Free-running or modulo up-count operation • Toggle any channel pin on overflow • TIMA counter stop and reset bits • Modular architecture expandable to eight channels Technical Data 170 Timer Interface Module A (TIMA) Figure 11 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 171
... TIMA clock pin, PTD6/TACLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIMA status and control register select the TIMA clock source. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Table Table 11-1. Pin Name Conventions TIMA Generic Pin Names: TACLK TACH0 ...
Page 172
... TOV3 ELS3B ELS3A CH3MAX CH3F MS3A CH3IE Timer Interface Module A (TIMA) TOF INTERRUPT LOGIC TOIE PTE2 PTE2/TACH0 LOGIC INTERRUPT LOGIC PTE3 PTE3/TACH1 LOGIC INTERRUPT LOGIC PTF0 PTF0/TACH2 LOGIC INTERRUPT LOGIC PTF1 PTF1/TACH3 LOGIC INTERRUPT LOGIC MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 173
... Reset: Read: Timer A Channel 1 Status $0029 and Control Register Write: (TASC1) Reset: Read: Timer A Channel 1 $002A Register High Write: (TACH1H) Reset: Figure 11-2. TIMA I/O Register Summary (Sheet MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Bit TOF 0 TOIE TSTOP 0 TRST Bit ...
Page 174
... Indeterminate after reset Bit Indeterminate after reset CH3F 0 CH3IE MS3A Bit Indeterminate after reset Bit Indeterminate after reset = Unimplemented Timer Interface Module A (TIMA Bit Bit 0 ELS2B ELS2A TOV2 CH2MAX Bit Bit 0 ELS3B ELS3A TOV3 CH3MAX Bit Bit 0 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 175
... MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor 11.5.3 Output When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value ...
Page 176
... I/O pin. NOTE: In buffered output compare operation, do not write new output compare values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered output compares. Technical Data 176 Timer Interface Module A (TIMA) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 177
... PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIMA channel registers produces a duty cycle of 128/256 or 50%. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Figure 11-3 shows, the output compare value in the TIMA channel OVERFLOW OVERFLOW PERIOD ...
Page 178
... Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. Technical Data 178 11.5.4 Pulse Width Modulation Timer Interface Module A (TIMA) (PWM). The pulses are MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 179
... In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. Writing to the active channel registers is the same as generating unbuffered PWM signals. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Timer Interface Module A (TIMA) Timer Interface Module A (TIMA) Technical Data 179 ...
Page 180
... Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. See Timer Interface Module A (TIMA) Table 11-3. Table 11-3. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 181
... The WAIT and STOP instructions puts the MCU in low-power- consumption standby modes. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Registers. TIMA overflow flag (TOF) — The TOF bit is set when the TIMA counter value rolls over to $0000 after matching the value in the TIMA counter modulo registers. The TIMA overflow interrupt enable bit, TOIE, enables TIMA overflow CPU interrupt requests ...
Page 182
... BCFE is at logic zero. After the break, doing the second step clears the status bit. Technical Data 182 8.8.3 SIM Break Flag Control Timer Interface Module A (TIMA) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 183
... TIMA Channel I/O Pins Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTF0/TACH2 and PTE3/TACH1 can be configured as buffered output compare or buffered PWM pins. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor 11.10.1 TIMA Status and Control or TACLK LMIN 1 ------------------------------------ - bus frequency bus frequency ÷ ...
Page 184
... Prescales the TIMA counter clock Address: Read: Write: Reset: Figure 11-4. TIMA Status and Control Register (TASC) Technical Data 184 $0020 Bit TOF 0 TOIE TSTOP 0 TRST Unimplemented Timer Interface Module A (TIMA Bit 0 0 PS2 PS1 PS0 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 185
... Setting the TSTOP and TRST bits simultaneously stops the TIMA counter at a value of $0000. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor 1 = TIMA counter has reached modulo value 0 = TIMA counter has not reached modulo value 1 = TIMA overflow interrupts enabled 0 = TIMA overflow interrupts disabled ...
Page 186
... Timer Interface Module A (TIMA) TIM Clock Source Internal Bus Clock ÷1 Internal Bus Clock ÷ 2 Internal Bus Clock ÷ 4 Internal Bus Clock ÷ 8 Internal Bus Clock ÷ 16 Internal Bus Clock ÷ 32 Internal Bus Clock ÷ 64 PTD6/TACLK Bit Bit MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 187
... Figure 11-7. TIMA Counter Modulo Register High (TAMODH) Address: Read: Write: Reset: Figure 11-8. TIMA Counter Modulo Register Low (TAMODL) NOTE: Reset the TIMA counter before writing to the TIMA counter modulo registers. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor $0023 Bit Bit ...
Page 188
... Figure 11-10. TIMA Channel 1 Status and Control Register (TASC1) Technical Data 188 $0026 Bit CH0F CH0IE MS0B MS0A $0029 Bit CH1F 0 CH1IE MS1A Timer Interface Module A (TIMA Bit 0 ELS0B ELS0A TOV0 CH0MAX Bit 0 ELS1B ELS1A TOV1 CH1MAX MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 189
... Reset clears the CHxF bit. Writing a logic one to CHxF has no effect. CHxIE — Channel x Interrupt Enable Bit This read/write bit enables TIMA CPU interrupts on channel x. Reset clears the CHxIE bit. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor $002C Bit CH2F CH2IE MS2B ...
Page 190
... I/O, and pin TACHx is available as a general-purpose I/O pin. ELSxB and ELSxA bits. Technical Data 190 Table 11-3. Table 11-3. Reset clears the MSxA bit. Table 11-3 shows how ELSxB and ELSxA work. Reset clears the Timer Interface Module A (TIMA) MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 191
... PWM signals to 100%. As Figure 11-13 is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Table 11-3. Mode, Edge, and Level Selection MSxA ELSxB ELSxA X 0 ...
Page 192
... PERIOD OUTPUT OUTPUT COMPARE COMPARE Figure 11-13. CHxMAX Latency $0027 Bit Bit Indeterminate after reset $0028 Bit Bit Indeterminate after reset Timer Interface Module A (TIMA) OVERFLOW OVERFLOW OUTPUT OUTPUT COMPARE COMPARE Bit Bit Bit Bit 0 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
Page 193
... Read: Write: Reset: Address: Read: Write: Reset: Address: Read: Write: Reset: Address: Read: Write: Reset: MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor $002A Bit Bit Indeterminate after reset Figure 11-16. TIMA Channel 1 Register High (TACH1H) $002B Bit Bit Indeterminate after reset Figure 11-17. TIMA Channel 1 Register Low (TACH1L) ...
Page 194
... Figure 11-20. TIMA Channel 3 Register High (TACH3H) Address: Read: Write: Reset: Figure 11-21. TIMA Channel 3 Register Low (TACH3L) Technical Data 194 $0030 Bit Bit Indeterminate after reset $0031 Bit Bit Indeterminate after reset Timer Interface Module A (TIMA Bit Bit Bit Bit 0 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
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... TIMB Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . 213 12.10.4 TIMB Channel Status and Control Registers . . . . . . . . . . . 214 12.10.5 TIMB Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 218 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 TIMB Counter Prescaler .197 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Output Compare ...
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... External TIMB clock input (4MHz maximum frequency) • Free-running or modulo up-count operation • Toggle any channel pin on overflow • TIMB counter stop and reset bits • Modular architecture expandable to eight channels Technical Data 196 Timer Interface Module B (TIMB) Figure 12 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
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... The prescaler select bits, PS[2:0], in the TIMB status and control register select the TIMB clock source. MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Table 12-1. The generic pin name appear in Table 12-1. Pin Name Conventions TIMB Generic Pin Names: ...
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... TOV3 ELS3B ELS3A CH3MAX CH3F MS3A CH3IE Timer Interface Module B (TIMB) TOF INTERRUPT LOGIC TOIE PTF4 PTF4/TBCH0 LOGIC INTERRUPT LOGIC PTF5 PTF5/TBCH1 LOGIC INTERRUPT LOGIC PTF2 PTF2/TBCH2T LOGIC INTERRUPT LOGIC PTF3 PTF3/TBCH3 LOGIC INTERRUPT LOGIC MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...
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... Reset: Read: Timer B Channel 1 Status $0048 and Control Register Write: (TBSC1) Reset: Read: Timer B Channel 1 $0049 Register High Write: (TBCH1H) Reset: Figure 12-2. TIMB I/O Register Summary (Sheet MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor Bit TOF 0 TOIE TSTOP 0 TRST Bit ...
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... Indeterminate after reset Bit Indeterminate after reset CH3F 0 CH3IE MS3A Bit Indeterminate after reset Bit Indeterminate after reset = Unimplemented Timer Interface Module B (TIMB Bit Bit 0 ELS2B ELS2A TOV2 CH2MAX Bit Bit 0 ELS3B ELS3A TOV3 CH3MAX Bit Bit 0 MC68HC908AB32 Rev. 1.1 — Freescale Semiconductor ...