MC68HC908GP32CFB Freescale Semiconductor, MC68HC908GP32CFB Datasheet
MC68HC908GP32CFB
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M68HC08 Microcontrollers MOTOROLA.COM/SEMICONDUCTORS MC68HC908GP32 MC68HC08GP32 Technical Data MC68HC908GP32/H Rev. 6, 8/2002 ...
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MC68HC908GP32 MC68HC08GP32 Technical Data Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any ...
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Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 Section 1. General Description . . . . . . . . . . . . . . . . . . . . 31 Section 2. Memory Map . . . . . . . ...
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List of Sections Section 20. Serial Peripheral Interface Module (SPI 303 Section 21. Timebase Module (TBM 335 Section 22. Timer Interface Module (TIM) ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 1.1 1.2 1.3 1.3.1 1.3.2 1.4 1.5 1.6 1.6.1 1.6.2 1.6.3 1.6.4 1.6.5 1.6.6 1.6.7 1.6.8 1.6.9 1.6.10 1.6.11 1.6.12 MC68HC908GP32 MC68HC08GP32 • MOTOROLA Section 1. General Description Contents . . . . . . . ...
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Table of Contents 2.1 2.2 2.3 2.4 2.5 3.1 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.4 3.4.1 3.4.2 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.7 3.7.1 3.7.2 3.8 3.8.1 3.8.2 3.9 Technical Data 6 Section 2. Memory Map Contents . ...
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MC68HC908GP32 MC68HC08GP32 • MOTOROLA Wait Mode . . . ...
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Table of Contents 4.4 4.4.1 4.4.2 4.4.2.1 4.4.2.2 4.4.2.3 4.4.2.4 4.4.2.5 4.4.2.6 4.4.2.7 4.4.2.8 4.4.2.9 4.4.2.10 4.4.2.11 4.4.3 4.4.3.1 4.4.3.2 4.4.3.3 5.1 5.2 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.5 5.6 5.6.1 5.6.2 5.7 Technical Data 8 Interrupts. . ...
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MC68HC908GP32 MC68HC08GP32 • MOTOROLA ADC Analog Power Pin (V ADC Voltage Reference High ...
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Table of Contents 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.7 7.8 7.8.1 7.8.2 7.8.3 7.9 7.9.1 7.9.2 7.9.3 Technical ...
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MC68HC908GP32 MC68HC08GP32 • MOTOROLA Section 8. Configuration Register (CONFIG) Contents . . . . . ...
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Table of Contents 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.5 10.6 10.6.1 10.6.2 10.7 10.8 10.9 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.8.1 11.9 11.10 Stop Mode . . . . . . . . . . . ...
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MC68HC908GP32 MC68HC08GP32 • MOTOROLA Section 12. External Interrupt (IRQ) Contents . . . . . . . ...
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Table of Contents 14.4.1 14.4.2 14.4.3 14.4.4 14.5 14.6 14.7 14.7.1 14.7.2 15.1 15.2 15.3 15.4 15.4.1 15.4.2 15.4.3 15.4.4 15.4.5 15.5 16.1 16.2 16.3 16.3.1 16.3.2 16.3.3 16.4 16.4.1 16.4.2 Technical Data 14 Polled LVI Operation . . . ...
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MC68HC908GP32 MC68HC08GP32 • MOTOROLA Port ...
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Table of Contents 18.5.3.1 18.5.3.2 18.5.3.3 18.5.3.4 18.5.3.5 18.5.3.6 18.5.3.7 18.5.3.8 18.6 18.6.1 18.6.2 18.7 18.8 18.8.1 18.8.2 18.9 18.9.1 18.9.2 18.9.3 18.9.4 18.9.5 18.9.6 18.9.7 19.1 19.2 19.3 19.3.1 19.3.2 19.3.3 19.4 19.4.1 19.4.2 Technical Data 16 Character Length ...
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MC68HC908GP32 MC68HC08GP32 • MOTOROLA Power-On Reset . . . ...
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Table of Contents 20.5.2 20.6 20.6.1 20.6.2 20.6.3 20.6.4 20.7 20.8 20.8.1 20.8.2 20.9 20.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . ...
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I/O Registers ...
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Table of Contents 22.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 359 22.10.4 TIM Channel Status and Control Registers . . . ...
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A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.8.1 A.8.2 A.8.3 A.8.4 A.9 MC68HC908GP32 MC68HC08GP32 • MOTOROLA Section 24. Mechanical Specifications Contents . . . . . . . . . . ...
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Table of Contents Technical Data 22 MC68HC908GP32 Table of Contents MC68HC08GP32 Rev. 6 • — MOTOROLA ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 Figure 1-1 1-2 1-3 1-4 1-5 2-1 2-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 5-1 5-2 5-3 5-4 6-1 6-2 6-3 6-4 6-5 6-6 6-7 MC68HC908GP32 MC68HC08GP32 • MOTOROLA Title MCU Block Diagram ...
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List of Figures Figure 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 14-2 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 14-3 LVI Status Register (LVISR) . ...
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List of Figures Figure 18-7 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 20-4 Transmission Format (CPHA = 311 20-5 CPHA/SS Timing . . . . . . . . ...
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List of Figures Figure 23-4 Typical High-Side Driver Characteristics – 23-5 Typical High-Side Driver Characteristics – 23-6 Typical High-Side Driver Characteristics – 23-7 Typical Low-Side Driver Characteristics – 23-8 Typical Low-Side Driver Characteristics – 23-9 Typical Low-Side Driver Characteristics – ...
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Technical Data – MC68HC908GP32 Table 2-1 4-1 4-2 5-1 5-2 7-1 7-3 7-2 10-1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 16-4 Port C Pin Functions ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 1.1 Contents 1.2 1.3 1.3.1 1.3.2 1.4 1.5 1.6 1.6.1 1.6.2 1.6.3 1.6.4 1.6.5 1.6.6 1.6.7 1.6.8 1.6.9 1.6.10 1.6.11 1.6.12 MC68HC908GP32 MC68HC08GP32 • MOTOROLA Section 1. General Description Introduction . . . . . . ...
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General Description 1.2 Introduction The MC68HC908GP32 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of ...
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MC68HC908GP32 MC68HC08GP32 • MOTOROLA Low-power design; fully static with stop and wait modes Standard low-power modes of operation: – Wait mode – Stop ...
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General Description • • • • • • • 1.3.2 Features of the CPU08 Features of the CPU08 include: • • • • • • • • • • Technical Data 34 Oscillator stop mode enable bit (OSCSTOPENB) in the ...
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MCU Block Diagram Figure 1-1 parentheses within a module block indicates the module name. Text in parentheses next to a signal indicates the module which uses the signal. MC68HC908GP32 MC68HC08GP32 • MOTOROLA shows the structure of the MC68HC908GP32. Text ...
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M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 64 BYTES USER FLASH — 32,256 BYTES USER RAM — 512 BYTES MONITOR ROM — 307 BYTES USER FLASH VECTOR SPACE — 36 BYTES CLOCK GENERATOR MODULE OSC1 ...
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Pin Assignments MC68HC908GP32 MC68HC08GP32 • MOTOROLA V (PLL) DDA 1 V (PLL) 2 SSA CGMXFC (PLL) 3 OSC2 4 OSC1 5 RST 6 PTC0 7 PTC1 8 PTC2 9 PTC3 10 PTC4 11 PTE0/TxD 12 PTE1/RxD 13 IRQ 14 ...
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General Description Technical Data 38 V (PLL) 1 DDA V (PLL) 2 SSA CGMXFC (PLL) 3 OSC2 4 OSC1 5 RST 6 PTC0 7 PTC1 8 PTC2 9 PTC3 10 PTC4 11 PTE0/TxD 12 PTE1/RxD 13 IRQ 14 PTD0/SS 15 ...
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Pin Functions Descriptions of the pin functions are provided here. 1.6.1 Power Supply Pins ( from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent ...
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General Description Use a high-frequency-response ceramic capacitor for C1 optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. 1.6.2 Oscillator Pins (OSC1 and OSC2) The OSC1 and ...
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CGM Power Supply Pins (V V DDA clock generator module (CGM). Connect the V voltage potential Section 7. Clock Generator Module 1.6.6 External Filter Capacitor Pin (CGMXFC) CGMXFC is an external filter capacitor connection for ...
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General Description 1.6.10 Port C I/O Pins (PTC6—PTC0) PTC6–PTC0 are general-purpose, bidirectional I/O port pins. Section 16. Input/Output (I/O) available on 44-pin QFP package. These port pins also have selectable pullups when configured for input mode. The pullups are disengaged ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 2.1 Contents 2.2 2.3 2.4 2.5 2.2 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in 2.3 Unimplemented Memory Locations Accessing an unimplemented location can cause an illegal address reset. ...
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Memory Map 2.4 Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation. In the reserved locations are marked with the word Reserved or with the letter R. 2.5 Input/Output (I/O) Section Most of the control, ...
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MC68HC908GP32 MC68HC08GP32 • MOTOROLA $0000 ↓ $003F $0040 ↓ $023F $0240 ↓ $7FFF $8000 ↓ $FDFF $FE00 $FE01 $FE02 $FE03 SIM Break Flag Control Register (SBFCR) $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B Break Status and Control Register (BRKSCR) ...
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Memory Map Note: $FFF6–$FFFD reserved for 8 security bytes Technical Data 46 $FE10 Unimplemented 16 Bytes ↓ Reserved for Compatibility with Monitor Code for A-Family Parts $FE1F $FE20 Monitor ROM ↓ 307 Bytes $FF52 $FF53 Unimplemented ↓ 43 Bytes $FF7D ...
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Addr. Register Name Read: Port A Data Register $0000 Write: (PTA) Reset: Read: Port B Data Register $0001 Write: (PTB) Reset: Read: Port C Data Register $0002 Write: (PTC) Reset: Read: Port D Data Register $0003 Write: (PTD) Reset: Read: ...
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Memory Map Addr. Register Name Read: $000A Unimplemented Write: Reset: Read: $000B Unimplemented Write: Reset: Read: Data Direction Register E $000C Write: (DDRE) Reset: Read: Port A Input Pullup Enable $000D Register Write: (PTAPUE) Reset: Read: Port C Input Pullup ...
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Addr. Register Name Read: SCI Control Register 2 $0014 Write: (SCC2) Reset: Read: SCI Control Register 3 $0015 Write: (SCC3) Reset: Read: SCI Status Register 1 $0016 Write: (SCS1) Reset: Read: SCI Status Register 2 $0017 Write: (SCS2) Reset: Read: ...
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Memory Map Addr. Register Name Read: Configuration Register 2 $001E (CONFIG2)† Write: Reset: Read: Configuration Register 1 $001F Write: † (CONFIG1) Reset: Read: Timer 1 Status and Control $0020 Register Write: (T1SC) Reset: Read: Timer 1 Counter $0021 Register High ...
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Addr. Register Name Read: Timer 1 Channel 1 Status $0028 and Control Register Write: (T1SC1) Reset: Read: Timer 1 Channel 1 $0029 Register High Write: (T1CH1H) Reset: Read: Timer 1 Channel 1 $002A Register Low Write: (T1CH1L) Reset: Read: Timer ...
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Memory Map Addr. Register Name Read: Timer 2 Channel 0 $0032 Register Low Write: (T2CH0L) Reset: Read: Timer 2 Channel 1 Status $0033 and Control Register Write: (T2SC1) Reset: Read: Timer 2 Channel 1 $0034 Register High Write: (T2CH1H) Reset: ...
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Addr. Register Name Read: Analog-to-Digital Status $003C and Control Register Write: (ADSCR) Reset: Read: Analog-to-Digital Data $003D Register Write: (ADR) Reset: Read: Analog-to-Digital Clock $003E Register Write: (ADCLK) Reset: Read: $003F Unimplemented Write: Reset: Read: SIM Break Status Register $FE00 ...
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Memory Map Addr. Register Name Read: Interrupt Status Register 3 $FE06 Write: (INT3) Reset: Read: $FE07 Reserved Write: Reset: Read: FLASH Control Register $FE08 Write: (FLCR) Reset: Read: Break Address $FE09 Register High Write: (BRKH) Reset: Read: Break Address $FE0A ...
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Vector Priority MC68HC908GP32 MC68HC08GP32 • MOTOROLA Table 2-1. Vector Addresses Vector Address Lowest $FFDC IF16 $FFDD $FFDE IF15 $FFDF $FFE0 IF14 $FFE1 $FFE2 IF13 $FFE3 $FFE4 IF12 $FFE5 $FFE6 IF11 $FFE7 $FFE8 IF10 $FFE9 $FFEA IF9 $FFEB $FFEC IF8 $FFED ...
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Memory Map Technical Data 56 MC68HC908GP32 Memory Map MC68HC08GP32 Rev. 6 • — MOTOROLA ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 3.1 Contents 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.4 3.4.1 3.4.2 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.7 3.7.1 3.7.2 3.8 3.8.1 3.8.2 3.9 3.9.1 3.9.2 3.10 3.10.1 MC68HC908GP32 MC68HC08GP32 • MOTOROLA Section 3. Low-Power Modes ...
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Low-Power Modes 3.10.2 3.11 3.11.1 3.11.2 3.12 3.12.1 3.12.2 3.13 3.13.1 3.13.2 3.14 3.14.1 3.14.2 3.15 3.16 3.2 Introduction The MCU may enter two low-power modes: wait mode and stop mode. They are common to all HC08 MCUs and are ...
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Stop Mode Stop mode is entered when a STOP instruction is executed. The CPU clock is disabled and the bus clock is disabled if the OSCSTOPENB bit in the CONFIG register logic 0. (See Register 3.3 ...
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Low-Power Modes 3.4.2 Stop Mode The break module is inactive in stop mode. A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. The STOP instruction does not affect break module register ...
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PLL without turning it off. Applications that require the PLL to wake the MCU from wait mode also can deselect the PLL output without turning off the PLL. 3.6.2 Stop Mode If the OSCSTOPEN bit in ...
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Low-Power Modes The STOP bit in the configuration register (CONFIG) enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit. 3.8 External Interrupt Module (IRQ) 3.8.1 ...
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Low-Voltage Inhibit Module (LVI) 3.10.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 3.10.2 Stop ...
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Low-Power Modes 3.12 Serial Peripheral Interface Module (SPI) 3.12.1 Wait Mode The SPI module remains active in wait mode. Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode. If SPI module functions ...
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Timebase Module (TBM) 3.14.1 Wait Mode The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase register is not accessible by the CPU. If the timebase functions are not required during wait mode, ...
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Low-Power Modes • • • • • • • • • Technical Data 66 External interrupt — A high-to-low transition on an external interrupt pin (IRQ pin) loads the program counter with the contents of locations: $FFFA and $FFFB; IRQ ...
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Exiting Stop Mode These events restart the system clocks and load the program counter with the reset vector or with an interrupt vector: • • • • MC68HC908GP32 MC68HC08GP32 • MOTOROLA – $FFE8 and $FFE9; SPI ...
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Low-Power Modes • Upon exit from stop mode, the system clocks begin running after an oscillator stabilization delay. A 12-bit stop recovery counter inhibits the system clocks for 4096 CGMXCLK cycles after the reset or external interrupt. The short stop ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 4.1 Contents 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.3.1 4.3.3.2 4.3.3.3 4.3.3.4 4.3.3.5 4.3.4 4.4 4.4.1 4.4.2 4.4.2.1 4.4.2.2 4.4.2.3 4.4.2.4 4.4.2.5 4.4.2.6 4.4.2.7 4.4.2.8 4.4.2.9 4.4.2.10 4.4.2.11 4.4.3 4.4.3.1 4.4.3.2 4.4.3.3 MC68HC908GP32 MC68HC08GP32 • MOTOROLA Section ...
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Resets and Interrupts 4.2 Introduction Resets and interrupts are responses to exceptional events during program execution. A reset re-initializes the MCU to its startup condition. An interrupt vectors the program counter to a service routine. 4.3 Resets A reset immediately ...
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Internal Reset Sources: • • • • • All internal reset sources pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external devices. The MCU is held in reset for an additional 32 CGMXCLK cycles ...
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Resets and Interrupts 4.3.3.1 Power-On Reset A power-on reset (POR internal reset caused by a positive transition on the V reset the MCU. This distinguishes between a reset and a POR. The POR is not a brown-out detector, ...
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COP Reset A COP reset is an internal reset caused by an overflow of the COP counter. A COP reset sets the COP bit in the system integration module (SIM) reset status register. To clear the COP counter and ...
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Resets and Interrupts 4.3.3.5 Illegal Address Reset An illegal address reset is an internal reset caused by opcode fetch from an unmapped address. An illegal address reset sets the ILAD bit in the SIM reset status register. A data fetch ...
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PIN — External Reset Flag COP — Computer Operating Properly Reset Bit ILOP — Illegal Opcode Reset Bit ILAD — Illegal Address Reset Bit MODRST — Monitor Mode Entry Module Reset Bit LVI — Low-Voltage Inhibit Reset Bit 4.4 Interrupts ...
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Resets and Interrupts • • STACKING ORDER After every instruction, the CPU checks all pending interrupts if the I bit is not set. If more than one interrupt is pending when an instruction is done, the highest priority interrupt is ...
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The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE: To maintain compatibility with the M6805 Family, the H register is not ...
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Resets and Interrupts YES Technical Data 78 FROM RESET YES BREAK INTERRUPT ? NO I BIT SET? I BIT SET? NO YES IRQ INTERRUPT ? NO YES CGM INTERRUPT ? NO YES OTHER INTERRUPTS ? NO STACK CPU REGISTERS LOAD ...
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Sources The sources in Reset SWI instruction IRQ pin CGM (PLL) TIM1 channel 0 TIM1 channel 1 TIM1 overflow TIM2 channel 0 TIM2 channel 1 TIM2 overflow SPI receiver full SPI overflow SPI mode fault SPI transmitter empty SCI ...
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Resets and Interrupts 4.4.2.1 SWI Instruction The software interrupt instruction (SWI) causes a non-maskable interrupt. NOTE: A software interrupt pushes PC onto the stack. An SWI does not push PC – hardware interrupt does. 4.4.2.2 Break Interrupt ...
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TIM2 TIM2 CPU interrupt sources: • • 4.4.2.7 SPI SPI CPU interrupt sources: • • • MC68HC908GP32 MC68HC08GP32 • MOTOROLA TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2 counter reaches the modulo value programmed ...
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Resets and Interrupts • 4.4.2.8 SCI SCI CPU interrupt sources: • • • • • Technical Data 82 Overflow bit (OVRF) — The OVRF bit is set if software does not read the byte in the receive data register before ...
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KBD0—KBD7 Pins A logic keyboard interrupt pin latches an external interrupt request. 4.4.2.10 ADC (Analog-to-Digital Converter) When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after ...
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Resets and Interrupts 4.4.3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. status register flags that they set. The interrupt status registers can be useful for debugging. Technical Data 84 Table 4-2 summarizes the ...
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Interrupt Status Register 1 Address: Read: Write: Reset: IF6–IF1 — Interrupt Flags 6–1 These flags indicate the presence of interrupt requests from the sources shown in Bit 1 and Bit 0 — Always read 0 4.4.3.2 Interrupt Status Register ...
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Resets and Interrupts 4.4.3.3 Interrupt Status Register 3 Address: Read: Write: Reset: IF16–IF15 — Interrupt Flags 16–15 This flag indicates the presence of an interrupt request from the source shown in Bits 7–2 — Always read 0 Technical Data 86 ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 Section 5. Analog-to-Digital Converter (ADC) 5.1 Contents 5.2 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.5 5.6 5.6.1 5.6.2 5.7 5.7.1 5.7.2 5.7.3 5.8 5.8.1 5.8.2 5.8.3 MC68HC908GP32 MC68HC08GP32 • MOTOROLA Introduction . . . . ...
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Analog-to-Digital Converter (ADC) 5.2 Introduction This section describes the 8-bit analog-to-digital converter (ADC). 5.3 Features Features of the ADC module include: • • • • • • 5.4 Functional Description The ADC provides eight pins for sampling external sources at ...
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INTERNAL DATA BUS INTERRUPT AIEN 5.4.1 ADC Port I/O Pins PTB7/AD7–PTB0/AD0 are general-purpose I/O (input/output) pins that share with the ADC channels. The channel select bits define which ADC channel/port pin will be used as the input signal. The ADC ...
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Analog-to-Digital Converter (ADC) 5.4.2 Voltage Conversion When the input voltage to the ADC equals V signal to $FF (full scale). If the input voltage equals V converts it to $00. Input voltages between V straight-line linear conversion. NOTE: Inside the ...
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Accuracy and Precision The conversion process is monotonic and has no missing codes. 5.5 Interrupts When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC conversion. A CPU interrupt is generated ...
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Analog-to-Digital Converter (ADC) 5.7.1 ADC Analog Power Pin (V The ADC analog portion uses V V DDAD be necessary to ensure clean V NOTE: For maximum noise immunity, route V capacitors as close as possible to the package. 5.7.2 ADC ...
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ADC Status and Control Register Function of the ADC status and control register (ADSCR) is described here. Address: Read: Write: Reset: COCO — Conversions Complete When the AIEN bit is a logic 0, the COCO is a read-only bit ...
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Analog-to-Digital Converter (ADC) ADCH4–ADCH0 — ADC Channel Select Bits ADCH4–ADCH0 form a 5-bit field which is used to select one of 16 ADC channels. Only eight channels, AD7–AD0, are available on this MCU. The channels are detailed in when using ...
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ADC Data Register One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC conversion completes. Address: Read: Write: Reset: 5.8.3 ADC Clock Register The ADC clock register (ADCLK) selects the clock ...
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Analog-to-Digital Converter (ADC) ADICLK — ADC Input Clock Select Bit ADICLK selects either the bus clock or CGMXCLK as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source. If the external ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 6.1 Contents 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.2 6.6.3 6.6.4 6.2 Introduction This section describes the break module. The break module can generate a break interrupt that stops normal ...
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Break Module (BRK) 6.3 Features Features of the break module include: • • • • 6.4 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to ...
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IAB15–IAB0 Figure 6-1. Break Module Block Diagram Addr. Register Name Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: Read: SIM Break Flag Control $FE03 Register Write: (SBFCR) Reset: Read: Break Address $FE09 Register High Write: (BRKH) Reset: Read: Break ...
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Break Module (BRK) 6.4.1 Flag Protection During Break Interrupts The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. 6.4.2 CPU During Break Interrupts The CPU starts a break ...
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Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. 6.6 Break Module Registers These registers control and monitor operation of the break module: • • • • • ...
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Break Module (BRK) BRKA — Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to ...
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Break Status Register The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from stop or wait mode. The flag is useful in applications requiring a return to stop or wait mode ...
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Break Module (BRK) 6.6.4 Break Flag Control Register The SIM break flag control register (SBFCR) contains a bit that enables software to clear status bits while the MCU break state. Address: Read: Write: Reset: BCFE — Break ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 Section 7. Clock Generator Module (CGMC) 7.1 Contents 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 7.6 7.6.1 7.6.2 7.6.3 7.6.4 ...
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Clock Generator Module (CGMC) 7.6.5 7.6.6 7.7 7.8 7.8.1 7.8.2 7.8.3 7.9 7.9.1 7.9.2 7.9.3 7.2 Introduction This section describes the clock generator module. The CGMC generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. ...
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Features Features of the CGMC include: • • • • • • • • 7.4 Functional Description The CGMC consists of three major submodules: • • • Figure 7-1 MC68HC908GP32 MC68HC08GP32 • MOTOROLA Phase-locked loop with output frequency in ...
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Clock Generator Module (CGMC) OSCILLATOR (OSC) OSC2 OSC1 SIMOSCEN (FROM SIM) OSCSTOPENB (FROM CONFIG) PHASE-LOCKED LOOP (PLL) CGMRDV REFERENCE DIVIDER R RDS3–RDS0 V DDA PHASE DETECTOR LOCK DETECTOR LOCK MUL11–MUL0 N CGMVDV FREQUENCY DIVIDER Technical Data 108 CGMRCLK BCS CGMXFC ...
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Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration ...
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Clock Generator Module (CGMC) The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range from roughly ...
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Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: • • 7.4.5 Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop ...
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Clock Generator Module (CGMC) The following conditions apply when the PLL is in automatic bandwidth control mode: • • • • • The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that ...
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The following conditions apply when in manual mode: • • • • • 7.4.6 Programming the PLL The following procedure shows how to program the PLL. NOTE: The round function in the following equations means that the real number should ...
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Clock Generator Module (CGMC) 4. Select a VCO frequency multiplier < N Technical Data 114 P, the power of two multiplier, and N, the range multiplier, are integers. In cases where desired bus frequency has ...
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Calculate and verify the adequacy of the VCO and bus 7. Select the VCO’s power-of-two range multiplier E, according to 8. Select a VCO linear range multiplier, L, where f 9. Calculate and verify the adequacy of the VCO ...
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Clock Generator Module (CGMC) 11. Program the PLL registers accordingly: NOTE: The values for and R can only be programmed when the PLL is off (PLLON = 0). Table 7-1 notation): 2.4576 MHz 4.9152 MHz 7.3728 ...
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Special Programming Exceptions The programming method described in does not account for three possible exceptions. A value of 0 for meaningless when used in the equations given. To account for these exceptions: • • ...
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Clock Generator Module (CGMC) 7.4.9 CGMC External Connections In its typical configuration, the CGMC requires up to nine external components. Five of these are for the crystal oscillator and two or four are for the PLL. The crystal oscillator is ...
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SIMOSCEN OSCSTOPENB (FROM CONFIG) OSC1 Note: Filter network in box can be replaced with a 0.47 µ F capacitor, but will degrade stability. Figure 7-2. CGMC External Connections 7.5 I/O Signals The following paragraphs describe the CGMC ...
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Clock Generator Module (CGMC) 7.5.3 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is connected to this pin. (See Figure NOTE: To prevent noise problems, ...
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Crystal Output Frequency Signal (CGMXCLK) CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (f Figure 7-2 OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown ...
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Clock Generator Module (CGMC) • • Figure 7-3 Addr. Register Name Read: PLL Control Register $0036 Write: (PCTL) Reset: Read: PLL Bandwidth Control $0037 Register Write: (PBWC) Reset: Read: PLL Multiplier Select High $0038 Register Write: (PMSH) Reset: Read: PLL ...
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PLL Control Register The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits. Address: Read: Write: Reset: PLLIE — ...
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Clock Generator Module (CGMC) PLLON — PLL On Bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See Circuit.) ...
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VPR1 and VPR0 — VCO Power-of-Two Range Select Bits These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction with L (See Programming the Register.) controls the hardware center-of-range frequency, f VPR1:VPR0 cannot be written when ...
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Clock Generator Module (CGMC) Address: Read: Write: Reset: AUTO — Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before turning on ...
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PLL Multiplier Select Register High The PLL multiplier select register high (PMSH) contains the programming information for the high byte of the modulo feedback divider. Address: Read: Write: Reset: MUL11–MUL8 — Multiplier Select Bits These read/write bits control the ...
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Clock Generator Module (CGMC) 7.6.4 PLL Multiplier Select Register Low The PLL multiplier select register low (PMSL) contains the programming information for the low byte of the modulo feedback divider. Address: Read: Write: Reset: MUL7–MUL0 — Multiplier Select Bits These ...
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PLL VCO Range Select Register NOTE: PMRS may be called PVRS on other HC08 derivatives. The PLL VCO range select register (PMRS) contains the programming information required for the hardware configuration of the VCO. Address: Read: Write: Reset: VRS7–VRS0 ...
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Clock Generator Module (CGMC) 7.6.6 PLL Reference Divider Select Register NOTE: PMDS may be called PRDS on other HC08 derivatives. The PLL reference divider select register (PMDS) contains the programming information for the modulo reference divider. Address: Read: Write: Reset: ...
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Interrupts When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables ...
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Clock Generator Module (CGMC) 7.8.2 Stop Mode If the OSCSTOPENB bit in the CONFIG register is cleared (default), then the STOP instruction disables the CGMC (oscillator and phase locked loop) and holds low all CGMC outputs (CGMXCLK, CGMOUT, and CGMINT). ...
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Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 7.9.1 Acquisition/Lock Time ...
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Clock Generator Module (CGMC) 7.9.2 Parametric Influences on Reaction Time Acquisition and lock times are designed short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and ...
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Choosing a Filter As described in external filter network is critical to the stability and reaction time of the PLL. The ...
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Clock Generator Module (CGMC) Technical Data 136 MC68HC908GP32 Clock Generator Module (CGMC) MC68HC08GP32 Rev. 6 • — MOTOROLA ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 Section 8. Configuration Register (CONFIG) 8.1 Contents 8.2 8.3 8.2 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers enable or disable these options: 8.3 Functional Description The configuration registers are used ...
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Configuration Register (CONFIG) NOTE FLASH device, the options except LVI5OR3 are one-time writeable by the user after each reset. The LVI5OR3 bit is one-time writeable by the user only after each POR (power-on reset). The CONFIG registers are ...
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SCIBDSRC — SCI Baud Rate Clock Source Bit SCIBDSRC controls the clock source used for the SCI. The setting of this bit affects the frequency at which the SCI operates. COPRS — COP Rate Select Bit COPRS selects the COP ...
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Configuration Register (CONFIG) SSREC — Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay. NOTE: Exiting stop mode by pulling reset will result in ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 Section 9. Computer Operating Properly (COP) 9.1 Contents 9.2 9.3 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 9.4.8 9.5 9.6 9.7 9.8 9.8.1 9.8.2 9.9 MC68HC908GP32 MC68HC08GP32 • MOTOROLA Introduction . . . . . ...
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Computer Operating Properly (COP) 9.2 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the ...
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The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 2 CGMXCLK cycles, depending on the state of the COP rate ...
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Computer Operating Properly (COP) 9.4.3 COPCTL Write Writing any value to the COP control register (COPCTL) Control of the prescaler. Reading the COP control register returns the low byte of the reset vector. 9.4.4 Power-On Reset The power-on reset (POR) ...
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COP Control Register The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte ...
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Computer Operating Properly (COP) 9.8.1 Wait Mode The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. 9.8.2 Stop Mode Stop mode turns off the ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 10.1 Contents 10.2 10.3 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.5 10.6 10.6.1 10.6.2 10.7 10.8 10.9 10.2 Introduction The M68HC08 CPU (central processor unit enhanced and fully object-code-compatible version of the M68HC05 CPU. ...
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Central Processor Unit (CPU) 10.3 Features • • • • • • • • • • • 10.4 CPU Registers Figure 10-1 the memory map. Technical Data 148 Object code fully upward-compatible with M68HC05 Family 16-bit stack pointer with stack ...
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Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: Write: Reset: MC68HC908GP32 MC68HC08GP32 • MOTOROLA ...
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Central Processor Unit (CPU) 10.4.2 Index Register The 16-bit index register allows indexed addressing of a 64-Kbyte memory space the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index ...
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Read: Write: Reset: NOTE: The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer ...
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Central Processor Unit (CPU) 10.4.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The ...
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I — Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU ...
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Central Processor Unit (CPU) C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such ...
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Stop Mode The STOP instruction: • • After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay. 10.7 CPU During Break Interrupts If a break module is present on the MCU, the CPU starts a ...
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Central Processor Unit (CPU) 10.8 Instruction Set Summary Table 10-1. Instruction Set Summary Source Operation Form ADC #opr ADC opr ADC opr ADC opr,X Add with Carry ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD ...
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Table 10-1. Instruction Set Summary (Continued) Source Operation Form BCLR n, opr Clear Bit BCS rel Branch if Carry Bit Set (Same as BLO) BEQ rel Branch if Equal Branch if Greater Than or Equal To BGE ...
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Central Processor Unit (CPU) Table 10-1. Instruction Set Summary (Continued) Source Operation Form BNE rel Branch if Not Equal BPL rel Branch if Plus BRA rel Branch Always BRCLR n,opr,rel Branch if Bit Clear BRN rel Branch ...
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Table 10-1. Instruction Set Summary (Continued) Source Operation Form CMP #opr CMP opr CMP opr CMP opr,X Compare A with M CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX Complement (One’s Complement) COM opr,X COM ,X ...
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Central Processor Unit (CPU) Table 10-1. Instruction Set Summary (Continued) Source Operation Form INC opr INCA INCX Increment INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X Jump JMP opr,X JMP ,X JSR opr JSR opr JSR ...
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Table 10-1. Instruction Set Summary (Continued) Source Operation Form NEG opr NEGA NEGX Negate (Two’s Complement) NEG opr,X NEG ,X NEG opr,SP NOP No Operation NSA Nibble Swap A ORA #opr ORA opr ORA opr ORA opr,X Inclusive OR A ...
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Central Processor Unit (CPU) Table 10-1. Instruction Set Summary (Continued) Source Operation Form SBC #opr SBC opr SBC opr SBC opr,X Subtract with Carry SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC Set Carry Bit SEI Set Interrupt Mask ...
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Table 10-1. Instruction Set Summary (Continued) Source Operation Form TST opr TSTA TSTX Test for Negative or Zero TST opr,X TST ,X TST opr,SP TSX Transfer SP to H:X TXA Transfer TXS Transfer H ...
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Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 11.1 Contents 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.8.1 11.9 11.10 Stop Mode . . . . . . . . . . . . . . . . . . . . . . ...
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FLASH Memory page. Hence the minimum erase page size is 128 bytes. Program and erase operation operations are facilitated through control bits in FLASH Control Register (FLCR). Details for these operations appear later in this section. The address ranges for ...
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MASS — Mass Erase Control Bit Setting this read/write bit configures the 32Kbyte FLASH array for mass erase operation. ERASE — Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit ...
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FLASH Memory 9. Clear the HVEN bit. 10. After a time, t NOTE: While these operations must be performed in the order shown, other unrelated operations may occur between the steps. 11.6 FLASH Mass Erase Operation Use this step-by-step procedure ...
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FLASH Program Operation Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $0080 and $XXC0. Use this step-by-step procedure to program a row of FLASH ...
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FLASH Memory NOTE: Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Do not ...
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Algorithm for programming a row (64 bytes) of FLASH memory NOTE: The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed to clearing PGM bit (step 7 to step ...
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FLASH Memory 11.8.1 FLASH Block Protect Register The FLASH block protect register (FLBPR) is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this ...
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Examples of protect start address: 11.9 Wait Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since ...
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FLASH Memory Technical Data 174 MC68HC908GP32 FLASH Memory MC68HC08GP32 Rev. 6 • — MOTOROLA ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 12.1 Contents 12.2 12.3 12.4 12.5 12.6 12.7 12.2 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. 12.3 Features Features of the IRQ module include: MC68HC908GP32 MC68HC08GP32 • MOTOROLA Section 12. External Interrupt ...
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External Interrupt (IRQ) 12.4 Functional Description A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one ...
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NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. RESET ACK VECTOR FETCH DECODER V DD INTERNAL PULLUP DEVICE IRQ Figure 12-1. IRQ Module Block Diagram Addr. Register Name Read: ...
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External Interrupt (IRQ) 12.5 IRQ Pin A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the ...
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NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. 12.6 IRQ Module During Break Interrupts The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the ...
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External Interrupt (IRQ) Address: Read: Write: Reset: IRQF — IRQ Flag Bit This read-only status bit is high when the IRQ interrupt is pending. ACK — IRQ Interrupt Request Acknowledge Bit Writing a logic 1 to this write-only bit clears ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 Section 13. Keyboard Interrupt Module (KBI) 13.1 Contents 13.2 13.3 13.4 13.5 13.6 13.6.1 13.6.2 13.7 13.8 13.8.1 13.8.2 13.2 Introduction The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are accessible via ...
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Keyboard Interrupt Module (KBI) 13.3 Features • • • • • 13.4 Functional Description Writing to the KBIE7–KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a ...
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KBD0 . TO PULLUP ENABLE . KB0IE . KBD7 TO PULLUP ENABLE KB7IE Figure 13-1. Keyboard Module Block Diagram Addr. Register Name Read: Keyboard Status $001A and Control Register Write: (INTKBSCR) Reset: Read: Keyboard Interrupt Enable $001B Register Write: (INTKBIER) ...
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Keyboard Interrupt Module (KBI) If the MODEK bit is set, the keyboard interrupt pins are both falling edge- and low-level sensitive, and both of the following actions must occur to clear a keyboard interrupt request: • • The vector fetch ...
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NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin. ...
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Keyboard Interrupt Module (KBI) 13.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. 13.6.1 Wait Mode The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status ...
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I/O Registers These registers control and monitor operation of the keyboard module: • • 13.8.1 Keyboard Status and Control Register The keyboard status and control register: • • • • Address: Read: Write: Reset: Figure 13-3. Keyboard Status and ...
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Keyboard Interrupt Module (KBI) ACKK — Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic 0. Reset clears ACKK. IMASKK — Keyboard Interrupt Mask Bit Writing a logic ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 14.1 Contents 14.2 14.3 14.4 14.4.1 14.4.2 14.4.3 14.4.4 14.5 14.6 14.7 14.7.1 14.7.2 14.2 Introduction This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the V voltage falls below the LVI ...
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Low-Voltage Inhibit (LVI) 14.4 Functional Description Figure 14-1 out of reset. The LVI module contains a bandgap reference circuit and comparator. Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor V enables the LVI module to generate ...
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An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices. Addr. Register Name Read: LVIOUT LVI Status Register $FE0C Write: (LVISR) Reset: 14.4.1 Polled LVI Operation In applications that can operate at V ...
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Low-Voltage Inhibit (LVI) 14.4.2 Forced Reset Operation In applications that require V enabling LVI resets allows the LVI module to reset the MCU when V falls below the V and LVIRSTD bits must be at logic 0 to enable the ...
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LVI Status Register The LVI status register (LVISR) indicates if the V detected below the V Address: Read: LVIOUT Write: Reset: LVIOUT — LVI Output Bit This read-only flag becomes set when the V V MC68HC908GP32 MC68HC08GP32 • MOTOROLA ...
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Low-Voltage Inhibit (LVI) 14.6 LVI Interrupts The LVI module does not generate interrupt requests. 14.7 Low-Power Modes The STOP and WAIT instructions put the MCU in low power- consumption standby modes. 14.7.1 Wait Mode If enabled, the LVI module remains ...
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Technical Data – MC68HC908GP32•MC68HC08GP32 15.1 Contents 15.2 15.3 15.4 15.4.1 15.4.2 15.4.3 15.4.4 15.4.5 15.5 15.2 Introduction This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the MCU through ...
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Monitor ROM (MON) 15.3 Features Features of the monitor ROM include: • • • • • • • • • • 15.4 Functional Description The monitor ROM receives and executes commands from a host computer. mode and communicate with a ...
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MC145407 + 10 µ µ DB- Notes: 1. For monitor mode entry when IRQ = V SW1: Position A — Bus clock = CGMXCLK ÷ ...
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Monitor ROM (MON) between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor. The monitor code has been updated from previous versions of the monitor code to allow enabling the PLL to ...