MC68HC908MR16CFU Freescale Semiconductor, MC68HC908MR16CFU Datasheet

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MC68HC908MR16CFU

Manufacturer Part Number
MC68HC908MR16CFU
Description
IC MCU 8MHZ 16K FLASH 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908MR16CFU

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
44
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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MC68HC908MR16CFU
Manufacturer:
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MC68HC908MR32
MC68HC908MR16
Data Sheet
M68HC08
Microcontrollers
MC68HC908MR32
Rev. 6.1
07/2005
freescale.com

Related parts for MC68HC908MR16CFU

MC68HC908MR16CFU Summary of contents

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MC68HC908MR32 MC68HC908MR16 Data Sheet M68HC08 Microcontrollers MC68HC908MR32 Rev. 6.1 07/2005 freescale.com ...

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...

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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005. All rights reserved. ...

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... IRQ) 19.6 FLASH Memory Characteristics — Updated table entries July, 6.1 Updated to meet Freescale identity guidelines. 2005 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 4 Description Page Number(s) 29 306 50 279 281 233 255 Throughout 207 291 292 Throughout Freescale Semiconductor ...

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... Chapter 15 Serial Peripheral Interface Module (SPI 195 Chapter 16 Timer Interface A (TIMA 215 Chapter 17 Timer Interface B (TIMB 235 Chapter 18 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Chapter 19 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Chapter 20 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 275 Appendix A MC68HC908MR16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 5 ...

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... List of Chapters MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 6 Freescale Semiconductor ...

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... FLASH Control Register 2.8.2 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.8.3 FLASH Mass Erase Operation 2.8.4 FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.8.5 FLASH Block Protection 2.8.6 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Chapter 1 General Description and and DDA SSAD and V ) ...

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... Manual and Automatic PLL Bandwidth Modes 4.3.2.4 Programming the PLL 4.3.2.5 Special Programming Exceptions 4.3.3 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.3.4 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 8 Chapter 3 Analog-to-Digital Converter (ADC DDAD ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SSAD ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 REFH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 REFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Chapter 4 Clock Generator Module (CGM) Freescale Semiconductor ...

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... Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.6 COPD (COP Disable 6.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.7 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 DDA Chapter 5 Configuration Register (CONFIG) Chapter 6 Computer Operating Properly (COP) 9 ...

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... LVI Trip Selection 9.4 LVI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.6 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.7 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 10 Chapter 7 Central Processor Unit (CPU) Chapter 8 External Interrupt (IRQ) Chapter 9 Low-Voltage Inhibit (LVI) Freescale Semiconductor ...

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... Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.6.1 Fault Condition Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.6.1.1 Fault Pin Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12.6.1.2 Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12.6.1.3 Manual Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Chapter 10 Input/Output (I/O) Ports (PORTS) Chapter 11 Power-On Reset (POR) Chapter 12 11 ...

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... SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 13.6 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 13.6.1 PTF5/TxD (Transmit Data 168 13.6.2 PTF4/RxD (Receive Data 169 13.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 13.7.1 SCI Control Register 169 13.7.2 SCI Control Register 171 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 12 Chapter 13 Freescale Semiconductor ...

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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.2 Features 195 15.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 15.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 15.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 15.5 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Chapter 14 System Integration Module (SIM) Chapter 15 13 ...

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... TIMA Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 16.7.2 TIMA Counter Registers 227 16.7.3 TIMA Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 16.7.4 TIMA Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 16.7.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 14 Chapter 16 Timer Interface A (TIMA) Freescale Semiconductor ...

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... Break Module Registers 253 18.2.3.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 18.2.3.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 18.2.3.3 Break Status Register 255 18.2.3.4 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Chapter 17 Timer Interface B (TIMB) Chapter 18 Development Support 15 ...

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... Ordering Information and Mechanical Specifications 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 20.2 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 20.3 64-Pin Plastic Quad Flat Pack (QFP 276 20.4 56-Pin Shrink Dual In-Line Package (SDIP 277 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 16 Chapter 19 Electrical Specifications Chapter 20 Appendix A MC68HC908MR16 Freescale Semiconductor ...

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... Illegal opcode or address detection with optional reset – Fault detection with optional PWM disabling 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 17 ...

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... Fast 8 × 8 multiply instruction • • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • C language support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908MR32. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 18 Freescale Semiconductor ...

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M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 112 BYTES USER FLASH — 32,256 BYTES USER RAM — 768 BYTES MONITOR ROM — 240 BYTES USER FLASH VECTOR SPACE — 46 BYTES OSC1 CLOCK GENERATOR OSC2 MODULE ...

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... PTC2 13 PTC3 14 PTC4 15 PTC5 16 Figure 1-2. 64-Pin QFP Pin Assignments MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 20 Figure 1-3 shows the 56-pin SDIP pin IRQ 48 PTF5/TxD 47 PTF4/RxD 46 PTF3/MISO 45 PTF2/MOSI 44 PTF1/SS 43 PTF0/SPSCK PTE7/TCH3A 39 PTE6/TCH2A 38 PTE5/TCH1A 37 PTE4/TCH0A 36 PTE3/TCLKA 35 PTE2/TCH1B 34 PTE1/TCH0B 33 Freescale Semiconductor SS DD ...

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... SSAD PTD0/FAULT1 PTD1/FAULT2 PTD2/FAULT3 PTD3/FAULT4 PTD4/IS1 Note: PTC1, PTE0, PTE1, PTE2, PTF0, PTF1, PTF2, and PTF3 are removed from this package. Figure 1-3. 56-Pin SDIP Pin Assignments MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor PTA2 1 PTA3 2 PTA4 3 PTA5 4 PTA6 5 ...

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... Decoupling of these pins should be per the digital supply. See MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 22 and MCU 0.1 µ 1–10 µ Figure 1-4. Power Supply Bypassing (CGM). Chapter 8 External Interrupt and V ) DDA SSAD Chapter 4 Clock Generator Module Figure 1 Chapter 14 System (IRQ). Freescale Semiconductor (CGM). ...

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... PWM Pins (PWM6–PWM1) PWM6–PWM1 are dedicated pins used for the outputs of the pulse-width modulator module (PWMMC). These are high-current sink pins. See and Chapter 19 Electrical Specifications. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor and V ) DDAD SSAD Chapter 3 Analog-to-Digital Converter ) REFH (ADC) ...

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... See Peripheral Interface Module (SPI), Chapter 10 Input/Output (I/O) Ports MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 24 Chapter 12 Pulse-Width Modulator for Motor (TIMA), Chapter 17 Timer Interface B Chapter 13 Serial Communications Interface Module (PORTS). (TIMB), and Chapter 10 Chapter 15 Serial (SCI), and Freescale Semiconductor ...

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... Some I/O bits are reserved. Writing to a reserved bit can have unpredictable effects on MCU operation. In register figures, reserved bits are marked with the letter R. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor (Figure 2-1) and in the I/O register summary (Figure ...

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... Memory Map Figure 2-1 shows the memory map for the MC68HC908MR32 while the memory map for the MC68HC908MR16 is shown in MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 26 Figure 2-2, contain most of the control, status, and data registers. Appendix A MC68HC908MR16 Freescale Semiconductor ...

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... Figure 2-1. MC68HC908MR32 Memory Map MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor I/O REGISTERS — 96 BYTES RAM — 768 BYTES UNIMPLEMENTED — 31,904 BYTES FLASH — 32,256 BYTES SIM BREAK STATUS REGISTER (SBSR) SIM RESET STATUS REGISTER (SRSR) ...

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... DDRC4 DDRC3 DDRC2 DDRC1 PTE4 PTE3 PTE2 PTE1 Unaffected by reset PTF4 PTF3 PTF2 PTF1 Unaffected by reset DDRE4 DDRE3 DDRE2 DDRE1 DDRF4 DDRF3 DDRF2 DDRF1 Bold = Buffered = Unimplemented Freescale Semiconductor Bit 0 PTA0 PTB0 PTC0 PTD0 R DDRA0 0 DDRB0 0 DDRC0 0 PTE0 PTF0 DDRE0 0 DDRF0 0 ...

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... See page 232. TIMA Channel 2 Status/Control $0019 Register (TASC2) See page 229 Unaffected X = Indeterminate Figure 2-2. Control, Status, and Data Registers Summary (Sheet MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Bit Read: TOF TOIE TSTOP Write: 0 Reset: ...

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... ISENS1 ISENS0 LDOK IPOL1 IPOL2 IPOL3 PRSC1 FINT2 FMODE2 FINT1 FPIN2 FFLAG2 FPIN1 DT5 DT4 DT3 DT2 FTACK2 OUT5 OUT4 OUT3 OUT2 Bold = Buffered = Unimplemented Freescale Semiconductor Bit 0 Bit 8 Bit 0 CH3MAX 0 Bit 8 Bit 0 COPD 0 PWMEN 0 PRSC0 0 FMODE1 0 FFLAG1 0 DT1 FTACK1 0 OUT1 0 ...

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... PWM 4 Value Register High $0030 (PVAL4H) See page 145. PWM 4 Value Register Low $0031 (PVAL4L) See page 145 Unaffected X = Indeterminate Figure 2-2. Control, Status, and Data Registers Summary (Sheet MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Bit Read Write: Reset ...

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... Bit 2 Bit Bit 4 Bit 3 Bit 2 Bit WAKE ILTY PEN ILIE TE RE RWU ORIE NEIE FEIE IDLE BKF Unaffected by reset Bold = Buffered = Unimplemented Freescale Semiconductor Bit 0 Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 Bit 0 1 Bit 0 1 PTY 0 SBK 0 PEIE RPF ...

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... TIMB Status/Control Register $0051 (TBSC) See page 244. TIMB Counter Register High $0052 (TBCNTH) See page 246 Unaffected X = Indeterminate Figure 2-2. Control, Status, and Data Registers Summary (Sheet MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Bit Read SCP1 Write Reset: ...

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... Bit 9 Bit 4 Bit 3 Bit 2 Bit 1 MS1A ELS1B ELS1A TOV1 Bit 12 Bit 11 Bit 10 Bit 9 Bit 4 Bit 3 Bit 2 Bit BCS XLD MUL4 VRS7 VRS6 VRS5 Bold = Buffered = Unimplemented Freescale Semiconductor Bit 0 Bit Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8 Bit 0 CH1MAX 0 Bit 8 Bit VRS4 0 ...

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... FLASH Block Protect Register $FF7E (FLBPR) See page 43. COP Control Register $FFFF (COPCTL) See page 77 Unaffected X = Indeterminate Figure 2-2. Control, Status, and Data Registers Summary (Sheet MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Bit Read Write: Reset: Read: POR ...

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... TIMA channel 3 vector (high) $FFE7 TIMA channel 3 vector (low) $FFE8 TIMA channel 2 vector (high) $FFE9 TIMA channel 2 vector (low) $FFEA TIMA channel 1 vector (high) $FFEB TIMA channel 1 vector (low) $FFEC TIMA channel 0 vector (high) $FFED TIMA channel 0 vector (low) Vector (1) (1) (1) (1) Freescale Semiconductor ...

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... Before processing an interrupt, the central processor unit (CPU) uses five bytes of the stack to save the contents of the CPU registers. For M68HC05 and M1468HC05 compatibility, the H register is not stacked. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Address $FFEE PWMMC vector (high) ...

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... Figure 2-3. FLASH Control Register (FLCR security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 38 NOTE NOTE NOTE HVEN ( Bit 0 MASS ERASE PGM Freescale Semiconductor ...

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... Any application can use this 4 ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE FLASH Memory (FLASH) 39 ...

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... When in monitor mode, with security sequence failed (see of any FLASH address. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 40 (1) within the FLASH memory address range. NOTE NOTE 18.3.2 Security), write to the FLASH block protect register instead Freescale Semiconductor ...

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... Do not exceed t Memory Characteristics. 1. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing PGM bit, must not exceed the maximum programming time, t MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE (1) . NOTE NOTE maximum, see 19 ...

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... SET HVEN BIT 6 WAIT FOR A TIME, t PGS 7 WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED 8 WAIT FOR A TIME, t PROG COMPLETED PROGRAMMING THIS ROW YES CLEAR PGM BIT WAIT FOR A TIME, t NVH CLEAR HVEN BIT WAIT FOR A TIME, t RCV END OF PROGRAMMING Freescale Semiconductor ...

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... With this mechanism, the protect start address can be XX00 and XX80 (128 bytes page boundaries) within the FLASH memory. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE Register. Once the FLBPR is programmed with a value other than , present on the IRQ pin. This voltage also ...

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... MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 44 16-BIT MEMORY ADDRESS FLBPR VALUE Start of Address of Protect Range The entire FLASH memory is protected. $8080 (1000 0000 1000 0000) $8100 (1000 0001 0000 0000) and so on... $FF00 (1111 1111 0000 0000) The entire FLASH memory is not protected. NOTE Freescale Semiconductor ...

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... ADC to select one of the 10 ADC channels as ADC voltage IN (ADCVIN). ADCVIN is converted by the successive approximation algorithm. When the conversion is completed, the ADC places the result in the ADC data register (ADRH and ADRL) and sets a flag or generates an interrupt. See MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Figure 3-2. 45 ...

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M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 112 BYTES USER FLASH — 32,256 BYTES USER RAM — 768 BYTES MONITOR ROM — 240 BYTES USER FLASH VECTOR SPACE — 46 BYTES OSC1 CLOCK GENERATOR OSC2 MODULE ...

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... All other input voltages will result in $3FF if greater than V if less than V . REFL Input voltage should not exceed the analog supply voltages. See 19.13 Analog-to-Digital Converter (ADC) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor ADC DATA REGISTERS ADC VOLTAGE IN ADVIN ADC ADC CLOCK CLOCK ...

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... ADRH. This may be useful if the result treated as an 8-bit result where the two least MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6 to17 ADC Cycles ADC Frequency ADC Cycles = µs 4 MHz/4 NOTE minimum and f ADIC 19.13 Analog-to-Digital Converter (ADC) maximum ADIC Freescale Semiconductor ...

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... Monotonicity The conversion process is monotonic and has no missing codes. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE Figure 3-3. IDEAL 8-BIT CHARACTERISTIC WITH QUANTIZATION = ±1/2 2 1/2 4 1/2 6 1/2 8 1/2 1 1/2 ...

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... Chapter 19 Electrical REFL NOTE pin to the same voltage DDAD for good results. DDAD pin to the same voltage SSAD . Connect the V pin to the same REFH . See Chapter 19 Electrical REFH pin to the same voltage potential as REFL Specifications. and V are tied REFL SSAD Freescale Semiconductor ...

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... These I/O registers control and monitor operation of the ADC: • ADC status and control register, ADSCR • ADC data registers, ADRH and ARDL • ADC clock register, ADCLK MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor and V REFH and V REFH REFL and V and must be placed as close as possible to the ...

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... MCU when the ADC is not used. Recovery from the disabled state requires one conversion cycle to stabilize. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6 AIEN ADCO ADCH4 ADCH3 NOTE Table 3-1. NOTE NOTE 2 1 Bit 0 ADCH2 ADCH1 ADCH0 Freescale Semiconductor ...

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... ADCH4 ADCH3 ATD9 is not available in the 56-pin SDIP package. 2. Used for factory testing any unused channels are selected, the resulting ADC conversion will be unknown. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Table 3-1. Mux Channel Select ADCH2 ADCH1 ADCH0 ...

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... ADRL is read. Until ADRL is read, all subsequent ADC results will be lost. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6 AD8 AD7 AD6 AD5 Unaffected by reset = Reserved Unaffected by reset = Reserved AD0 Unaffected by reset = Reserved 2 1 Bit 0 AD4 AD3 AD2 Bit 0 0 AD9 AD8 Bit Freescale Semiconductor ...

Page 55

... ADIV2:ADIV0 — ADC Clock Prescaler Bits ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 3-2 ADIV2 X = don’t care MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor AD6 AD5 ...

Page 56

... ADC data registers is controlled by these modes of operation. Reset returns right-justified mode 8-bit truncation mode 01 = Right justified mode 10 = Left justified mode 11 = Left justified sign data mode MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6 correct operation can be guaranteed. See ADIC Characteristics. ADIV[2:0] Freescale Semiconductor ...

Page 57

... Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from CGMOUT. Figure 4-1 shows the structure of the CGM. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 57 ...

Page 58

... ACQ Write: R Reset Read: MUL7 MUL6 MUL5 Write: Reset Reserved Figure 4-2. CGM I/O Register Summary CGMXCLK TO SIM A CGMOUT ÷ SIM B S* *WHEN CGMOUT = B USER MODE PTC2 MONITOR MODE CGMINT PLLF BCS XLD MUL4 VRS7 VRS6 VRS5 Freescale Semiconductor Bit VRS4 0 ...

Page 59

... The filter can make fast or slow corrections depending on its mode, described in 4.3.2.2 Acquisition and Tracking the reference frequency determines the speed of the corrections and the stability of the PLL. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor , (4.9152 MHz) times a linear factor ( RCLK VCLK ...

Page 60

... Register read-only indicator of the mode of the 4.3.2.2 Acquisition and Tracking . For more information, see UNT . For more information, see UNL 4.5.1 PLL Control Register. Register. 4.5.2 PLL Circuit. If 4.6 Modes. , and is cleared when TRK 4.8 , and is cleared Lock 4.8 Freescale Semiconductor ...

Page 61

... N. Round the result to the nearest integer. 32 MHz Example MHz 4. Calculate the VCO frequency, f Example: f MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor , after entering tracking mode before selecting the PLL as the AL Table 4-1 lists the variables used and their meaning. Table 4-1. Variable Definitions Definition ...

Page 62

... MHz 4 MHz , calculate the VCO linear range multiplier, L. The linear range NOM f VCLK ) ( f NOM = 7 MHz . The center-or-range frequency is the midpoint VRS VRS NOM f NOM | ≤ VCLK 2 CAUTION 4.3.2.4 Programming the PLL Circuit. . BUSDES BUSDES does not account for possible Freescale Semiconductor or ...

Page 63

... Pierce oscillator guidelines and may not S be required for all ranges of operation, especially with high-frequency crystals. Refer to the crystal manufacturer’s data for more information. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor CGMXCLK OSC2 V SS ...

Page 64

... The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and PLL. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 64 NOTE NOTE should be placed as close to the CGMXFC F connection DDA NOTE for routing information pin to the same voltage DDA Freescale Semiconductor ...

Page 65

... When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only. 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Figure 4-3 shows only the logical relation of CGMXCLK to OSC1 4.5.1 PLL Control Register 4 ...

Page 66

... PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6 PLLF 1 PLLON BCS Figure 4-5. PLL Control Register (PCTL) NOTE NOTE 2 1 Bit 4.3.3 Base Clock Selector 4.3.3 Base Clock Freescale Semiconductor ...

Page 67

... In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode Tracking mode 0 = Acquisition mode MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Circuit ...

Page 68

... Table 4-2. VCO Frequency Multiplier (N) Selection MUL7:MUL6:MUL5:MUL4 0000 0001 0010 0011 1101 1110 1111 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6 MUL6 MUL5 MUL4 VRS7 4.3.2.4 Programming the PLL. A value the multiplier select bits VCO Frequency Multiplier ( Bit 0 VRS6 VRS5 VRS4 Freescale Semiconductor ...

Page 69

... PLL without turning it off. Applications that require the PLL to wake the MCU from wait mode also can deselect the PLL output without turning off the PLL. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE . See 4 ...

Page 70

... MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 70 – f DES 4.3.2.3 Manual and Automatic PLL Bandwidth , of not more than ±100 percent. In automatic – f )/f DES ORIG DES 4.3.2.3 Manual and Automatic PLL Bandwidth TRK , of not more than ±100 )/f ORIG DES . Lock time is Lock Modes. RDV Freescale Semiconductor . . ...

Page 71

... Correct selection of filter capacitor, C • Room temperature operation • Negligible external leakage on C • Negligible noise MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 4.8.3 Choosing a Filter DDA Time, the external filter capacitor, C ⎛ ⎞ V DDA ⎜ ⎟ ...

Page 72

... Lock Circuit) because the factors described in is the K factor when the PLL ACQ A certain number of clock TRK , is required to ascertain that the TRK , is an integer ACQ /f . Also, since TRK RDV before selecting the PLL Lock 4.8.2 Parametric Freescale Semiconductor , ...

Page 73

... V DD nine consecutive central processor unit (CPU) cycles. Once an LVI reset occurs, the MCU remains in reset until V MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE 5-1. , and remains at or below that level for at least LVRx rises to a voltage ...

Page 74

... COPD disables the COP module. See 1 = COP module disabled 0 = COP module enabled MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6 TOPNEG INDEP LVIRST (PWMMC). (PWMMC). (PWMMC). (LVI). Chapter 9 Low-Voltage Inhibit (LVI) Chapter 6 Computer Operating Properly 2 1 Bit 0 LVIPWR STOPE COPD Chapter 12 Chapter 12 (PWMMC). (COP). Freescale Semiconductor ...

Page 75

... RESET VECTOR FETCH COPCTL WRITE COPD (FROM CONFIG) RESET COPCTL WRITE Note 1. See 14.3.2 Active Resets from Internal MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor SIM 13-BIT SIM COUNTER COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER Sources. Figure 6-1. COP Block Diagram ...

Page 76

... SIM counter. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 76 Bit Read: Write: Reset: Figure 6-2. COP I/O Register Summary Register. NOTE Figure 6-1. 6.4 COP Control Low byte of reset vector Clear COP counter Unaffected by reset Register) clears the COP Freescale Semiconductor Bit 0 ...

Page 77

... Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor (CONFIG ...

Page 78

... Computer Operating Properly (COP) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 78 Freescale Semiconductor ...

Page 79

... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 7.3 CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 79 ...

Page 80

... STACK POINTER (SP) 0 PROGRAM COUNTER (PC CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers Unaffected by reset Figure 7-2. Accumulator ( Figure 7-3. Index Register (H: Bit 0 Bit Freescale Semiconductor ...

Page 81

... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor ...

Page 82

... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6 NOTE 2 1 Bit Freescale Semiconductor ...

Page 83

... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Arithmetic/Logic Unit (ALU) 83 ...

Page 84

... EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 – – IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 – – IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 Freescale Semiconductor ...

Page 85

... CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Description ← (PC rel ? ( – – – – – – REL PC ← (PC rel ? IRQ = 1 – – – – – – REL PC ← ...

Page 86

... DIR INH 4A 1 INH 5A 1 – – – IX1 SP1 9E6A ff 5 INH 52 7 IMM DIR EXT IX2 – IX1 SP1 9EE8 ff 4 SP2 9ED8 DIR INH 4C 1 INH 5C 1 – – – IX1 SP1 9E6C ff 5 Freescale Semiconductor ...

Page 87

... ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Effect on CCR Description ← Jump Address – – – – – – PC ← (PC Push (PCL); SP ← (SP) – 1 – ...

Page 88

... IX2 IX1 SP1 9EE2 ff 4 SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF IMM DIR EXT IX2 IX1 SP1 9EE0 ff 4 SP2 9ED0 Freescale Semiconductor ...

Page 89

... Memory location N Negative bit 7.8 Opcode Map See Table 7-2. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Description ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) – – 1 – – – INH SP ← (SP) – 1; Push (CCR) SP ← ...

Page 90

Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...

Page 91

... IRQ module. ACK1 IRQ LATCH MODE1 Addr. Register Name IRQ Status/Control Register $003F (ISCR) See page 94. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor CLR Q SYNCHRO- NIZER IRQ IMASK1 HIGH VOLTAGE DETECT Figure 8-1. IRQ Module Block Diagram Bit Read: 0 ...

Page 92

... If the IRQ1 mask bit, IMASK1, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. • Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, the IRQ1 latch remains set. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 92 NOTE Figure 8-3.) Freescale Semiconductor ...

Page 93

... FROM RESET YES I BIT SET? INTERRUPT? FETCH NEXT INSTRUCTION INSTRUCTION? INSTRUCTION? MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NO YES NO STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR YES SWI NO YES RTI UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 8-3. IRQ Interrupt Flowchart ...

Page 94

... Figure 8-4. IRQ Status and Control Register (ISCR) ACK1 — IRQ Interrupt Request Acknowledge Bit Writing a logic 1 to this write-only bit clears the IRQ latch. ACK1 always reads as logic 0. Reset clears ACK1. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 94 NOTE IRQF Bit 0 0 IMASK1 MODE1 ACK1 Freescale Semiconductor ...

Page 95

... IRQ interrupt requests on falling edges only IRQF — IRQ Flag This read-only bit acts as a status flag, indicating an IRQ event occurred External IRQ event occurred External IRQ event did not occur. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor IRQ Status and Control Register 95 ...

Page 96

... External Interrupt (IRQ) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 96 Freescale Semiconductor ...

Page 97

... LVItrip = 0 DD LOW V DD DETECTOR V < LVItrip = 1 DD TRPSEL FROM LVISCR MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor voltage falls to the LVI trip voltage. DD Chapter 5 Configuration Register LVIPWR FROM CONFIG V DD DIGITAL FILTER ANLGTRIP LVIOUT Figure 9-1. LVI Module Block Diagram Figure 9-2) ...

Page 98

... LVRX must remain at or below V LVRX for only one CPU cycle to bring the MCU out of reset. TRPSEL in the . NOTE rises above a voltage LVRX polling the DD (CONFIG). TRPSEL . LVRX for nine or more consecutive CPU cycles. 19.5 DC Freescale Semiconductor . LVHX Bit ...

Page 99

... Wait Mode The WAIT instruction puts the MCU in low power-consumption standby mode. With the LVIPWR bit in the configuration register programmed to 1, the LVI module is active after a WAIT instruction. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor voltages below the ...

Page 100

... MCU out of wait mode. 9.7 Stop Mode If enabled, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 100 Freescale Semiconductor ...

Page 101

... Port C Data Register $0002 (PTC) See page 106. Port D Data Register $0003 (PTD) See page 107. Data Direction Register A $0004 (DDRA) See page 103. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE Bit Read: PTA7 PTA6 PTA5 Write: Reset: Read: PTB7 ...

Page 102

... Reset Reserved DDRB4 DDRB3 DDRB2 DDRB1 DDRC4 DDRC3 DDRC2 DDRC1 Unimplemented PTE4 PTE3 PTE2 PTE1 Unaffected by reset PTF4 PTF3 PTF2 PTF1 Unaffected by reset DDRE4 DDRE3 DDRE2 DDRE1 DDRF4 DDRF3 DDRF2 DDRF1 Unimplemented Freescale Semiconductor Bit 0 DDRB0 0 DDRC0 0 PTE0 PTF0 DDRE0 0 DDRF0 0 ...

Page 103

... Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from Figure 10-4 shows the port A I/O logic. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor PTA6 PTA5 ...

Page 104

... A pins. Table 10-1. Port A Pin Functions Accesses to DDRA I/O Pin Mode Read/Write (2) DDRA[7:0] Input, Hi-Z Output DDRA[7: PTB6 PTB5 PTB4 PTB3 Unaffected by reset PTAx Accesses to PTA Read Write (3) Pin PTA[7:0] PTA[7:0] PTA[7: Bit 0 PTB2 PTB1 PTB0 Freescale Semiconductor ...

Page 105

... The data latch can always be written, regardless of the state of its data direction bit. DDRB Bit PTB Bit ( don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor DDRB5 DDRB4 DDRB3 NOTE ...

Page 106

... Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 106 PTC6 PTC5 PTC4 PTC3 Unaffected by reset DDRC5 DDRC4 DDRC3 NOTE 2 1 Bit 0 PTC2 PTC1 PTC0 2 1 Bit 0 DDRC2 DDRC1 DDRC0 Freescale Semiconductor ...

Page 107

... Reserved Figure 10-11. Port D Data Register (PTD) PTD[6:0] — Port D Data Bits These read/write bits are software programmable. Reset has no effect on port D data. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor DDRCx RESET PTCx Figure 10-10. Port C I/O Circuit Table 10-3 summarizes the operation of the port C pins ...

Page 108

... MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 108 Figure 10-12. Port D Input Circuit Table 10-4 Table 10-4. Port D Pin Functions Accesses to PTD Pin Mode Read (2) Pin Input, Hi PTE6 PTE5 PTE4 PTE3 Unaffected by reset NOTE PTDx summarizes the operation of the Write (3) PTD[6: Bit 0 PTE2 PTE1 PTE0 Freescale Semiconductor ...

Page 109

... The data latch can always be written, regardless of the state of its data direction bit. DDRE Bit PTE Bit ( don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor DDRE5 DDRE4 DDRE3 NOTE ...

Page 110

... Avoid glitches on port F pins by writing to the port F data register before changing data direction register F bits from MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 110 PTF5 PTF4 PTF3 R Unaffected by reset NOTE DDRF5 DDRF4 DDRF3 NOTE 2 1 Bit 0 PTF2 PTF1 PTF0 2 1 Bit 0 DDRF2 DDRF1 DDRF0 Freescale Semiconductor ...

Page 111

... don’t care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor DDRFx RESET PTFx Figure 10-18. Port F I/O Circuit Table 10-6 summarizes the operation of the port F pins. Table 10-6. Port F Pin Functions ...

Page 112

... Input/Output (I/O) Ports (PORTS) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 112 Freescale Semiconductor ...

Page 113

... POR drives its output low. The POR is not a brown-out detector, low-voltage detector, or glitch detector. V completely reset the microcontroller unit (MCU). To detect power-loss conditions, use a low-voltage inhibit module (LVI) or other suitable circuit. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor at the POR must go DD 113 ...

Page 114

... Power-On Reset (POR) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 114 Freescale Semiconductor ...

Page 115

... Complementary mode featuring: – Dead-time insertion – Separate top/bottom pulse width correction via current sensing or programmable software bits MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor ) and a programmable prescaler. The highest resolution for MHz). The highest resolution for center-aligned operation is OP Figure 12-3 ...

Page 116

M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 112 BYTES USER FLASH — 32,256 BYTES USER RAM — 768 BYTES MONITOR ROM — 240 BYTES USER FLASH VECTOR SPACE — 46 BYTES OSC1 CLOCK GENERATOR OSC2 MODULE ...

Page 117

... Fault Status Register $0023 (FSR) See page 152. Fault Acknowledge Register $0024 (FTACK) See page 153. Figure 12-3. Register Summary (Sheet MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 8 PWM CHANNELS 1 AND 2 PWM CHANNELS 3 AND 4 PWM CHANNELS 5 AND 6 12 TIMEBASE Bit ...

Page 118

... Bit 11 Bit 10 Bit Bit 4 Bit 3 Bit 2 Bit Bit 12 Bit 11 Bit 10 Bit Bit 4 Bit 3 Bit 2 Bit Bold = Buffered X = Indeterminate Freescale Semiconductor Bit 0 OUT1 0 Bit 8 0 Bit 0 0 Bit 8 X Bit 0 X Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 Bit 8 0 Bit 0 0 ...

Page 119

... See page 145. Dead-Time Write-Once $0036 Register (DEADTM) See page 150. PWM Disable Mapping $0037 Write-Once Register (DISMAP) See page 150. Figure 12-3. Register Summary (Sheet MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Bit Read: Bit 15 Bit 14 Bit 13 Write: Reset ...

Page 120

... The PWM period will equal: [(timer modulus) x (PWM clock period) x 2]. UP/DOWN COUNTER MODULUS = 4 PWM = 0 PWM = 1 PWM = 2 PWM = 3 PWM = 4 Figure 12-4. Center-Aligned PWM (Positive Polarity) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 120 PERIOD = 8 X (PWM CLOCK PERIOD MHz) as shown in OP Freescale Semiconductor ...

Page 121

... Center-aligned operation versus edge-aligned operation is determined by the option EDGE. See Functional Description. UP-ONLY COUNTER Figure 12-5. Edge-Aligned PWM (Positive Polarity) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor (timer modulus) x (PWM clock period) MODULUS = 4 PERIOD = 4 X (PWM CLOCK PERIOD) PWM = 0 ...

Page 122

... MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 122 Table 12-1. PWM Prescaler PWM Clock Frequency Table 12-2. PWM Reload Frequency PWM Reload Frequency 00 Every PWM cycle 01 Every 2 PWM cycles 10 Every 4 PWM cycles 11 Every 8 PWM cycles / Table 12-2. When a reload cycle Freescale Semiconductor ...

Page 123

... LDOK bit is set. Even not set, an interrupt will occur if the PWMINT bit is set. To prevent this, the software should clear the PWMINT bit before enabling the PWM module. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE RELOAD CHANGE RELOAD ...

Page 124

... LDOK = 0 LDOK = 0 MODULUS = 3 MODULUS = 3 MODULUS = 3 PWM VALUE = 2 PWM VALUE = 2 PWM VALUE = 1 PWMF SET PWMF SET PWMF SET LDOK = 0 MODULUS = 3 PWM VALUE = 1 PWMF SET LDOK = 1 LDOK = 0 MODULUS = 1 MODULUS = 2 PWM VALUE = 1 PWMF SET PWMF SET LDOK = 0 MODULUS = 3 PWM VALUE = 1 PWMF SET Freescale Semiconductor ...

Page 125

... PWM pins. Table 12-3. PWM Data Overflow and Underflow Conditions PWMVALxH:PWMVALxL $0000–$0FFF $1000–$7FFF $8000–$FFFF MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor LDFQ1:LDFQ0 = 00 (RELOAD EVERY CYCLE) LDOK = 1 LDOK = 1 MODULUS = 4 MODULUS = 2 PWM VALUE = 2 ...

Page 126

... PWMS 1 AND 2 PWMS 3 AND 4 PWMS 5 AND 6 Figure 12-12. Complementary Pairing PWM 1 3 PWM 2 4 Figure 12-13. Typical AC Motor Drive 5.2 Functional Description). If Figure 12-12. Operation of PWM1 PIN PWM2 PIN PWM3 PIN PWM4 PIN PWM5 PIN PWM6 PIN PWM 5 PWM 6 Freescale Semiconductor TO MOTOR ...

Page 127

... MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 12-13, if PWM1 and PWM2 were on at the same time, large currents 12-14. Current sensing determines which PWM value of a PWM generator 12 ...

Page 128

... DEAD-TIME PREDT (TOP) POSTDT (TOP) OUTX SELECT MUX PWM (TOP) DEAD-TIME PREDT (TOP) POSTDT (TOP) OUTX SELECT Figure 12-14. Dead-Time Generators TOP PWM1 (PWM1) BOTTOM PWM2 (PWM2) TOP PWM3 (PWM3) BOTTOM PWM4 (PWM4) TOP PWM5 (PWM5) BOTTOM PWM6 (PWM6) Freescale Semiconductor ...

Page 129

... UP/DOWN COUNTER MODULUS = 3 PWM VALUE = 1 PWM1 W/ NO DEAD-TIME PWM2 W/ NO DEAD-TIME PWM1 W/ DEAD-TIME = 2 PWM2 W/ 2 DEAD-TIME = 2 Figure 12-16. Dead-Time at Duty Cycle Boundaries MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor PWM VALUE = PWM VALUE = 1 PWM VALUE = Output Control PWM VALUE = ...

Page 130

... However, when dead-time is inserted, the motor voltage is allowed to float momentarily during the dead-time interval, creating a distortion in the motor current waveform. This distortion is aggravated by dissimilar turn-on and turn-off delays of each of the transistors. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 130 PWM VALUE = 3 PWM VALUE = PWM VALUE = Freescale Semiconductor ...

Page 131

... PWMs are PWMs 2, 4, and 6. Current Sense Pin or Bit IS1 or IPOL1 IS1 or IPOL1 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Figure 12-13, for a given top/bottom transistor pair, only one Table NOTE Figure 12-19 for current convention. In Table 12-4. Current Sense Pins ...

Page 132

... Bits IPOL1, IPOL2, and IPOL3 used for correction Current sensing on pins IS1, IS2, and IS3 occurs during the dead-time. Current sensing on pins IS1, IS2, and IS3 occurs at the half cycle in center-aligned mode and at the end of the cycle in edge-aligned mode. NOTE Freescale Semiconductor ...

Page 133

... Both bits are found in the CONFIG register, which is a write-once register. This reduces the chances of the software inadvertently changing the polarity of the PWM signals and possibly damaging the motor drive hardware. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor PWM VALUE REG IS1 NEGATIVE IS1 POSITIVE PWM = 2 ...

Page 134

... PWM >= 4 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 134 EDGE-ALIGNED POSITIVE POLARITY UP-ONLY COUNTER MODULUS = 4 PWM <= 0 PWM = 1 PWM = 2 PWM = 3 PWM >= 4 EDGE-ALIGNED NEGATIVE POLARITY UP-ONLY COUNTER MODULUS = 4 PWM <= 0 PWM = 1 PWM = 2 PWM = 3 PWM >= 4 Figure 12-21. PWM Polarity Freescale Semiconductor ...

Page 135

... PWM cycle. To avoid an unexpected dead-time occurrence recommended that the OUTx bits be cleared prior to entering and prior to exiting individual PWM output control mode. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Figure 12-22 ...

Page 136

... DEAD-TIME INSERTED BECAUSE DEAD-TIME INSERTED WHEN OUTCTL WAS SET, THE BECAUSE OUT1 TOGGLES, STATE OF OUT1 WAS SUCH THAT DIRECTING PWM1 TO PWM1 WAS DIRECTED TO TOGGLE TOGGLE 2 DEAD-TIME INSERTED DUE TO CLEARING OF OUT1 BIT 2 NO DEAD-TIME INSERTED BECAUSE OUT1 IS NOT TOGGLING Freescale Semiconductor ...

Page 137

... Automatic mode is selected by setting the FMODEx bit in the fault control register. Manual mode is selected when FMODEx is clear. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor shows the structure of the PWM disabling scheme. While the PWM pins Figure 12-25 ...

Page 138

... FFLAG2 MANUAL MODE R FINT2 CYCLE START FMODE1 AUTO FPIN1 MODE ONE S Q SHOT FFLAG1 MANUAL MODE R FINT1 Figure 12-26. PWM Disabling Scheme SOFTWARE X DISABLE BANK X DISABLE FAULT PIN 2 DISABLE INTERRUPT REQUEST FAULT PIN 1 DISABLE S Q BANK X DISABLE R INTERRUPT REQUEST Freescale Semiconductor ...

Page 139

... The FFLAGx bit is cleared by writing the corresponding FTACKx bit. • The FINTx bit is cleared. This will not clear the FFLAGx bit. • A reset automatically clears all four interrupt latches. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 ...

Page 140

... FILTERED FAULT PIN PWM(S) ENABLED Figure 12-29. PWM Disabling in Manual Mode (Example 1) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 140 PWM(S) DISABLED (INACTIVE) NOTE Figure 12-30. PWM(S) ENABLED PWM(S) DISABLED FFLAGX CLEARED PWM(S) ENABLED 12-29. A fault condition on pins 2 Freescale Semiconductor ...

Page 141

... Due to the absence of periodic PWM cycles, fault conditions are cleared upon each CPU cycle and the PWM outputs are re-enabled, provided all fault clearing conditions are satisfied. DISABLE BIT PWM(S) ENABLED MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor PWM(S) DISABLED FFLAGX CLEARED PWM(S) DISABLED Figure 12-31. PWM Software Disable ...

Page 142

... The PWMF flag and pending CPU interrupts are NOT cleared when PWMEN = 0. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 142 NOTE 12.9.2 PWM Counter Modulo 12-32. DRIVE ACCORDING TO PWM VALUE, POLARITY, AND DEAD-TIME Figure 12-32. PWMEN and PWM Pins NOTE Registers. HI-Z IF OUTCTL = 0 Freescale Semiconductor ...

Page 143

... Bit 7 Read: 0 Write: Reset Unimplemented Figure 12-33. PWM Counter Register High (PCNTH) Address: $0027 Bit 7 Read: Bit 7 Write: Reset Unimplemented Figure 12-34. PWM Counter Register Low (PCNTL) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 12-34 Bit Bit 6 Bit 5 ...

Page 144

... However, the dead-time constraints and fault conditions will still be guaranteed. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 144 and Figure 12-36 Bit Indeterminate Bit 6 Bit 5 Bit 4 Bit NOTE 2 1 Bit 0 Bit 10 Bit 9 Bit Bit 0 Bit 2 Bit 1 Bit Freescale Semiconductor ...

Page 145

... To avoid erroneous PWM pulses, this value is buffered and will not be used by the PWM generator until the LDOK bit has been set and the next PWM load cycle begins. When reading these registers, the value read is the buffer (not necessarily the value the PWM generator is currently using). MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor ...

Page 146

... ISENS1 and ISENS0 — Current Sense Correction Bits These read/write bits select the top/bottom correction scheme as shown in MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 146 DISY PWMINT PWMF ISENS1 NOTE NOTE 2 1 Bit 0 ISENS0 LDOK PWMEN Table 12-7. Freescale Semiconductor ...

Page 147

... Initialization and the PWMEN 1 = PWM generator and PWM pins enabled 0 = PWM generator and PWM pins disabled MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Table 12-7. Correction Methods Correction Method Bits IPOL1, IPOL2, and IPOL3 are used for correction. ...

Page 148

... MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 148 NOTE LDFQ0 IPOL1 IPOL2 Bold = Buffered NOTE Table 12-8. PWM Reload Frequency PWM Reload Frequency NOTE 2 1 Bit 0 IPOL3 PRSC1 PRSC0 Table 12-8. Every PWM cycle Every 2 PWM cycles Every 4 PWM cycles Every 8 PWM cycles Freescale Semiconductor ...

Page 149

... When reading these bits, the value read is the buffer value (not necessarily the value the PWM generator is currently using). Prescaler Bits PRSC1 and PRSC0 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE NOTE NOTE NOTE Table 12-9. PWM Prescaler ...

Page 150

... MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 150 Bit 6 Bit 5 Bit 4 Bit Protection. After this register is written for the first time, it cannot Bit 6 Bit 5 Bit 4 Bit FINT3 FMODE3 FINT2 Bit 0 Bit 2 Bit 1 Bit Bit 0 Bit 2 Bit 1 Bit Bit 0 FMODE2 FINT1 FMODE1 Freescale Semiconductor ...

Page 151

... FMODE1 —Fault Mode Selection for Fault Pin 1 Bit (automatic versus manual mode) This read/write bit allows the user to select between automatic and manual mode faults. For further descriptions of each mode, see 1 = Automatic mode 0 = Manual mode MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 12.6 Fault Protection. 12.6 Fault Protection. 12.6 Fault Protection ...

Page 152

... FPIN1 — State of Fault Pin 1 Bit This read-only bit allows the user to read the current state of fault pin Fault pin logic Fault pin logic 0. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 152 FPIN3 FFLAG3 FPIN2 Unaffected 2 1 Bit 0 FFLAG2 FPIN1 FFLAG1 Freescale Semiconductor ...

Page 153

... DT4 — Dead-Time 4 Bit Current sensing pin IS2 is monitored immediately before dead-time ends due to the assertion of PWM4. DT3 — Dead-Time 3 Bit Current sensing pin IS2 is monitored immediately before dead-time ends due to the assertion of PWM3. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor DT6 ...

Page 154

... Independent Mode 1 — PWM1 is active. 0 — PWM1 is inactive. 1 — PWM2 is active. 0 — PWM2 is inactive. 1 — PWM3 is active. 0 — PWM3 is inactive. 1 — PWM4 is active. 0 — PWM4 is inactive. 1 — PWM5 is active. 0 — PWM5 is inactive. 1 — PWM6 is active. 0 — PWM6 is inactive. Freescale Semiconductor ...

Page 155

... OP • Edge-aligned mode: The time it takes the PWM counter to count up (modulus/f 12-47. PWM CLOCK CYCLE Figure 12-47. PWM Clock Cycle and PWM Cycle Definitions MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor ) OP Figure 12-47. Center-Aligned Mode PWM CYCLE (OR PERIOD) Edge-Aligned Mode ...

Page 156

... LDFQ1:LDFQ0 = 01 — Reload Every Two Cycles RELOAD NEW MODULUS, PRESCALER, & PWM VALUES IF LDOK = 1 Figure 12-48. PWM Load Cycle/Frequency Definition MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 156 PWM LOAD CYCLE (1/PWM LOAD FREQUENCY) RELOAD NEW MODULUS, PRESCALER, & PWM VALUES IF LDOK = 1 Freescale Semiconductor ...

Page 157

... Receiver full – Idle receiver input – Receiver overrun – Noise error – Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 157 ...

Page 158

M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 112 BYTES USER FLASH — 32,256 BYTES USER RAM — 768 BYTES MONITOR ROM — 240 BYTES USER FLASH VECTOR SPACE — 46 BYTES OSC1 CLOCK GENERATOR OSC2 MODULE ...

Page 159

... SCI DATA REGISTER RECEIVE PTF4/RxD SHIFT REGISTER SCTIE TCIE SCRIE ILIE TE RE RWU SBK WAKEUP CONTROL f ÷ MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor INTERNAL BUS SCTE TC SCRF OR IDLE LOOPS RECEIVE FLAG CONTROL CONTROL BKF ENSCI RPF PRE- BAUD RATE ...

Page 160

... ORIE NEIE FEIE IDLE BKF Unaffected by reset 0 SCP0 SCR2 SCR1 Unaffected Figure 13-4. POSSIBLE PARITY NEXT BIT START STOP BIT 7 BIT BIT POSSIBLE PARITY NEXT BIT START BIT BIT 7 BIT 8 STOP BIT Freescale Semiconductor Bit 0 PTY 0 SBK 0 PEIE RPF SCR0 0 ...

Page 161

... SCI transmitter. PRE- BAUD ÷ 4 SCALER DIVIDER SCP1 SCP0 SCR2 SCR1 SCR0 PEN PTY TRANSMITTER CPU INTERRUPT REQUEST MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor INTERNAL BUS ÷ 16 SCI DATA REGISTER 11-BIT TRANSMIT SHIFT REGISTER TXINV M PARITY GENERATION ...

Page 162

... Clears the SCI data register (SCDR) • Clears the R8 bit in SCC3 • Sets the break flag bit (BKF) in SCS2 • May set the overrun (OR), noise flag (NF), parity error (PE), or reception-in-progress flag (RPF) bits MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 162 Freescale Semiconductor ...

Page 163

... SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. 13.3.3 Receiver Figure 13-6 shows the structure of the SCI receiver. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE 1. Functional Description 163 ...

Page 164

... INTERNAL BUS SCR2 SCR1 SCR0 BAUD ÷ 16 DIVIDER DATA H 8 RECOVERY ALL 0s WAKEUP LOGIC PARITY CHECKING IDLE ILIE SCRF SCRIE OR ORIE NF NEIE FE FEIE PE PEIE SCI DATA REGISTER 11-BIT RECEIVE SHIFT REGISTER RWU SCRF IDLE R8 ILIE SCRIE OR ORIE NF NEIE FE FEIE PE PEIE Freescale Semiconductor ...

Page 165

... To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 13-1 summarizes the results of the start bit verification samples. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor START BIT START BIT START BIT ...

Page 166

... Table 13-2. Data Bit Recovery Data Bit Samples Determination 000 0 001 0 010 0 011 1 100 0 101 1 110 1 111 1 NOTE Table 13-3. Stop Bit Recovery Framing Samples Error Flag 000 1 001 1 010 1 011 0 100 1 101 0 110 0 111 0 Noise Flag Noise Flag Table 13-3 Noise Flag Freescale Semiconductor ...

Page 167

... SCDR. The previous character remains in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI error CPU interrupt requests. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NOTE Functional Description 167 ...

Page 168

... The PTF5/TxD pin is the serial data output from the SCI transmitter. The SCI shares the PTF5/TxD pin with port F. When the SCI is enabled, the PTF5/TxD pin is an output regardless of the state of the DDRF5 bit in data direction register F (DDRF). MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 168 Freescale Semiconductor ...

Page 169

... SCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode. Reset clears the LOOPS bit Loop mode enabled 0 = Normal operation enabled MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor ENSCI ...

Page 170

... Changing the PTY bit in the middle of a transmission or reception can generate a parity error. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 170 NOTE Table 13-4. When enabled, the parity function Figure 13-4. Reset clears the PEN bit. NOTE Table 13-4. The Freescale Semiconductor ...

Page 171

... This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears the TCIE bit enabled to generate CPU interrupt requests not enabled to generate CPU interrupt requests MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Table 13-4. Character Format Selection Character Format Start Data ...

Page 172

... No break characters being transmitted Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK too early causes the SCI to send a break character instead of a preamble. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 172 NOTE NOTE NOTE Freescale Semiconductor ...

Page 173

... This read/write bit enables SCI receiver CPU interrupt requests generated by the parity error bit, PE. See 13.7.4 SCI Status Register 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor ...

Page 174

... SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF Received data available in SCDR 0 = Data not available in SCDR MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 174 SCRF IDLE Bit Freescale Semiconductor ...

Page 175

... OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flag-clearing sequence reads byte 3 in the SCDR instead of byte 2. BYTE 1 READ SCS1 READ SCDR BYTE 1 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor NORMAL FLAG CLEARING SEQUENCE BYTE 2 BYTE 3 READ SCS1 SCRF = 1 SCRF = 1 ...

Page 176

... SCDR. Once cleared, BKF can become set again only after logic 1s again appear on the PTF4/RxD pin followed by another break character. Reset clears the BKF bit Break character detected break character detected MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 176 Bit 0 0 BKF RPF Freescale Semiconductor ...

Page 177

... Read: 0 Write: R Reset Reserved Figure 13-15. SCI Baud Rate Register (SCBR) SCP1 and SCP0 — SCI Baud Rate Prescaler Bits These read/write bits select the baud rate prescaler divisor as shown in and SCP0. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor ...

Page 178

... MHz and the CGM set for MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 178 Table 13-6. SCI Baud Rate Selection Baud Rate Divisor (BD) 000 001 010 011 100 101 110 111 ----------------------------------- - × × 4.9152 MHz. OP Table 13-6. Reset clears 128 Freescale Semiconductor ...

Page 179

... MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Baud Rate SCR2:SCR1:SCR0 Divisor (BD) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 000 ...

Page 180

... Serial Communications Interface Module (SCI) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 180 Freescale Semiconductor ...

Page 181

... Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Figure 14-1. Table 14-1. Signal Name Conventions Description 181 ...

Page 182

... SIMOSCEN (TO CGM) COP CLOCK CGMXCLK (FROM CGM) CGMOUT (FROM CGM) INTERNAL CLOCKS LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE Figure 14-2. This clock (CGM). Freescale Semiconductor ...

Page 183

... Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See timing. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor CGMXCLK CLOCK A CGMOUT ÷ ...

Page 184

... Figure 14-3. External Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST INTERNAL RESET LVI POR Figure 14-4. Sources of Internal Reset NOTE RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES Figure 14-5. Internal Reset Timing VECT H VECT L Figure 14-5. VECTOR HIGH Freescale Semiconductor ...

Page 185

... The COP module is disabled if the RST pin or the IRQ pin is held at V The COP module can be disabled only through combinational logic conditioned with the high voltage MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 32 32 CYCLES CYCLES Figure 14-6 ...

Page 186

... External reset has no effect on the SIM counter. The SIM counter is free-running after all reset states. For counter control and internal reset recovery sequences, see MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 186 on the RST pin disables the COP module. 14.3.2 Active Resets from Internal voltage falls to the V DD LVRX 19.5 DC Electrical Sources. Freescale Semiconductor ...

Page 187

... CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). See MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Figure 14-9 shows interrupt recovery timing. SP – – ...

Page 188

... FROM RESET YES BREAK OR SWI I BIT SET? INTERRUPT BIT SET? NO YES INTERRUPT? NO STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES UNSTACK CPU REGISTERS INSTRUCTION? NO EXECUTE INSTRUCTION Figure 14-8. Interrupt Processing SET I BIT Freescale Semiconductor ...

Page 189

... If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor SP – – – 1 ...

Page 190

... MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 190 WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 14-11. Wait Mode Entry Timing show the timing for wait recovery. $6E0B $6E0C $00FF $A6 $A6 $01 $0B Figure 14-11 SAME SAME SAME $00FE $00FD $00FC $6E Freescale Semiconductor shows ...

Page 191

... This status bit is useful in applications requiring a return to wait mode after exiting from a break interrupt. Clear SBSW by writing a logic 0 to it. Reset clears SBSW Wait mode was exited by break interrupt Wait mode was not exited by break interrupt. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 32 32 CYCLES CYCLES ...

Page 192

... Last reset caused by the MENRST circuit 0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 192 PIN COP ILOP ILAD Bit 0 MENRST LVI Freescale Semiconductor ...

Page 193

... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor ...

Page 194

... System Integration Module (SIM) MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 194 Freescale Semiconductor ...

Page 195

... The generic pin names appear in the text that follows. Table 15-1 Generic Pin Names: Full Pin Names: MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor shows the full names of the SPI I/O pins. Table 15-1. Pin Name Conventions MISO MOSI PTF3/MISO ...

Page 196

M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT CONTROL AND STATUS REGISTERS — 112 BYTES USER FLASH — 32,256 BYTES USER RAM — 768 BYTES MONITOR ROM — 240 BYTES USER FLASH VECTOR SPACE — 46 BYTES OSC1 CLOCK GENERATOR OSC2 MODULE ...

Page 197

... CLOCK DIVIDER ÷ 32 ÷ 128 CLOCK SPMSTR SPE SELECT SPR1 TRANSMITTER CPU INTERRUPT REQUEST RECEIVER/ERROR CPU INTERRUPT REQUEST MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor Figure 15-3 INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER RECEIVE DATA REGISTER SPR0 ...

Page 198

... NOTE 15.12.1 SPI Control Figure 15-4. MISO MISO MOSI MOSI SPSCK SPSCK Register. Through the SPSCK pin, the baud-rate generator of the CPOL CPHA SPWOM SPE MODF SPTE MODFEN SPR1 Unaffected by reset Register. SLAVE MCU SHIFT REGISTER SS Freescale Semiconductor Bit 0 SPTIE 0 SPR0 ...

Page 199

... SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or low clock and has no significant effect on the transmission format. MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 Freescale Semiconductor 15.6.2 Mode Fault 15.5 Transmission Formats. ...

Page 200

... MISO/MOSI MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1 200 NOTE Figure 15- MSB BIT 6 BIT 5 BIT 4 BIT 3 MSB BIT 6 BIT 5 BIT 4 BIT 3 BYTE 1 BYTE 2 Figure 15-6. CPHA/SS Timing BIT 2 BIT 1 LSB BIT 2 BIT 1 LSB BYTE 3 Freescale Semiconductor ...

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