MC68HC11E1CFN3 Freescale Semiconductor, MC68HC11E1CFN3 Datasheet - Page 108

• Manufacturer Part Number: MC68HC11E1CFN3
• Description: IC MCU 3MHZ 512 EEPROM 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E1CFN3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 16 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Resets and Interrupts
Data Sheet
108
sequence results in which all I/O pins and functions are also restored to their initial
states.
To use the IRQ pin as a means of recovering from stop, the I bit in the CCR must
be clear (IRQ not masked). The XIRQ pin can be used to wake up the MCU from
stop regardless of the state of the X bit in the CCR, although the recovery sequence
depends on the state of the X bit. If X is set to 0 (XIRQ not masked), the MCU starts
up, beginning with the stacking sequence leading to normal service of the XIRQ
request. If X is set to 1 (XIRQ masked or inhibited), then processing continues with
the instruction that immediately follows the STOP instruction, and no XIRQ
interrupt service is requested or pending.
Because the oscillator is stopped in stop mode, a restart delay may be imposed to
allow oscillator stabilization upon leaving stop. If the internal oscillator is being
used, this delay is required; however, if a stable external oscillator is being used,
the DLY control bit can be used to bypass this startup delay. The DLY control bit is
set by reset and can be optionally cleared during initialization. If the DLY equal to
0 option is used to avoid startup delay on recovery from stop, then reset should not
be used as the means of recovering from stop, as this causes DLY to be set again
by reset, imposing the restart delay. This same delay also applies to power-on
reset, regardless of the state of the DLY control bit, but does not apply to a reset
while the clocks are running.
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Resets and Interrupts
M68HC11E Family — Rev. 5
MOTOROLA