MC68HC11E1CFN3 Freescale Semiconductor, MC68HC11E1CFN3 Datasheet - Page 110

IC MCU 3MHZ 512 EEPROM 52-PLCC

MC68HC11E1CFN3

Manufacturer Part Number
MC68HC11E1CFN3
Description
IC MCU 3MHZ 512 EEPROM 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC11E1CFN3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
22
Number Of Timers
16 bit
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

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Parallel Input/Output (I/O) Ports
Data Sheet
110
NOTE:
Alternate function:
DDRA7 — Data Direction for Port A Bit 7
Even when port A bit 7 is configured as an output, the pin still drives the input to
the pulse accumulator.
PAEN — Pulse Accumulator System Enable Bit
PAMOD — Pulse Accumulator Mode Bit
PEDGE — Pulse Accumulator Edge Control Bit
DDRA3 — Data Direction for Port A Bit 3
I4/O5 — Input Capture 4/Output Compare 5 Bit
RTR[1:0] — RTI Interrupt Rate Select Bits
Overridden if an output compare function is configured to control the PA7 pin
The pulse accumulator uses port A bit 7 as the PAI input, but the pin can also
be used as general-purpose I/O or as an output compare.
Refer to
Refer to
Refer to
This bit is overridden if an output compare function is configured to control the
PA3 pin.
Refer to
Refer to
Address:
Address:
And/or:
Reset:
Reset:
Read:
Write:
Read:
Write:
0 = Input
1 = Output
0 = Input
1 = Output
Freescale Semiconductor, Inc.
Figure 6-2. Pulse Accumulator Control Register (PACTL)
For More Information On This Product,
I = Indeterminate after reset
Section 9. Timing
Section 9. Timing
Section 9. Timing
Section 9. Timing
Section 9. Timing
DDRA7
$1000
$1026
OC1
Bit 7
PA7
Bit 7
PAI
0
I
Figure 6-1. Port A Data Register (PORTA)
Parallel Input/Output (I/O) Ports
Go to: www.freescale.com
PAEWN
OC2
OC1
PA6
6
0
6
0
PAMOD
OC3
OC1
System.
System.
System.
System.
System.
PA5
5
0
5
0
PEDGE
OC4
OC1
PA4
4
0
4
0
IC4/OC5
DDRA3
OC1
PA3
3
3
0
I
I4/O5
M68HC11E Family — Rev. 5
PA2
IC1
2
2
0
I
RTR1
PA1
IC2
1
1
0
I
MOTOROLA
RTR0
Bit 0
Bit 0
PA0
IC3
0
I

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